公开(公告)号：US06809541B2

公开(公告)日：2004-10-26

申请号：US10151028

申请日：2002-05-21

Applicant: Lin-Kai Bu ,  Kun-Cheng Hung

Inventor： Lin-Kai Bu ,  Kun-Cheng Hung

IPC: G01R3126

CPC classification number: G01R31/318511 ,  G01R31/318505

Abstract: A testing method and a testing a voltages apparatus embedded in the scribe line on a wafer are disclosed, for testing the to be measured from a die on a wafer. The testing apparatus includes a multiplexer and a comparator. The multiplexer receives the voltages to be measured and outputs a multiplexing or selected voltage according to a selection signal. The comparator receives a reference voltage and the multiplexing voltage and then outputs a digital result by comparing the reference voltage, and the multiplexing voltage. The digital result can be applied to a digital testing machine, such that testing speed is increased and testing cost is decreased. Moreover, the testing apparatus embedded in the scribe lines has the capability to compensate for the comparator's offset, and accordingly, the testing reliability is also improved.

Abstract translation: 公开了一种测试方法和测试嵌入在晶片上的划线中的电压装置，用于从晶片上的模具测试待测量的测试方法。 测试装置包括多路复用器和比较器。 多路复用器接收要测量的电压，并根据选择信号输出复用或选择的电压。 比较器接收参考电压和多路复用电压，然后通过比较参考电压和多路复用电压输出数字结果。 数字结果可以应用于数字测试机，从而提高测试速度，降低测试成本。 此外，嵌入划线中的测试装置具有补偿比较器偏移的能力，因此也提高了测试可靠性。

公开(公告)号：US06806515B2

公开(公告)日：2004-10-19

申请号：US10044950

申请日：2002-01-15

Applicant: Chuan-Cheng Hsiao ,  Lin-Kai Bu ,  Kun-Cheng Hung ,  Chien-Pin Chen

Inventor： Chuan-Cheng Hsiao ,  Lin-Kai Bu ,  Kun-Cheng Hung ,  Chien-Pin Chen

IPC: H01L31072

CPC classification number: H01L27/0207 ,  G02F1/1368 ,  G09G3/3688 ,  G09G2310/027

Abstract: A layout structure of a decoder with m*n nodes and the method thereof are provided. The nodes comprise a plurality of transistor nodes and a plurality of channel nodes. The manufacturing method of the transistor node comprises forming a gate, a first source/drain region and a second source/drain region. The channel node is fabricated by forming a channel. The channel, the first source/drain region and the second source/drain region are formed at the same time with the same material. The decoder circuit with smaller width is accomplished without additional mask in the invention.

Abstract translation: 提供具有m * n个节点的解码器的布局结构及其方法。 节点包括多个晶体管节点和多个信道节点。 晶体管节点的制造方法包括形成栅极，第一源极/漏极区域和第二源极/漏极区域。 通道节点通过形成通道来制造。 通道，第一源极/漏极区域和第二源极/漏极区域同时用相同的材​​料形成。 具有较小宽度的解码器电路在本发明中实现而不需要额外的掩模。

公开(公告)号：US20060202870A1

公开(公告)日：2006-09-14

申请号：US11364725

申请日：2006-02-27

Applicant: Chih-Chung Tsai ,  Kun-Cheng Hung

Inventor： Chih-Chung Tsai ,  Kun-Cheng Hung

IPC: H03M7/00

CPC classification number: H01L27/0207 ,  H01L27/092 ,  H03M1/664 ,  H03M1/76

Abstract: A decoder of a digital-to-analog converter is disclosed. In the present invention, the gamma voltage selection is controlled by a reduced number of NMOS and PMOS transistors according to the characteristic of the NMOS and PMOS transistor, such that the layout area of the switch array is reduced. Moreover, a N-type buried diffusion (BDN) layer and a P-type buried diffusion (BDP) layer are adopted to replace the contacts in the layout of conventional decoder, such that the layout can be simplified and the bump pad pitch thereof can be decreased.

Abstract translation: 公开了一种数模转换器的解码器。 在本发明中，根据NMOS和PMOS晶体管的特性，通过减少数量的NMOS和PMOS晶体管来控制伽马电压选择，使得开关阵列的布局面积减小。 此外，采用N型埋入扩散（BDN）层和P型埋入扩散（BDP）层来代替传统解码器布局中的触点，从而可以简化布局，并且其凸点焊盘间距可以 减少

公开(公告)号：US07053632B1

公开(公告)日：2006-05-30

申请号：US11117938

申请日：2005-04-28

Applicant: Shen-Yao Liang ,  Hung-Sung Chu ,  Kun-Cheng Hung

Inventor： Shen-Yao Liang ,  Hung-Sung Chu ,  Kun-Cheng Hung

IPC: G01R27/26 ,  H02J7/04

CPC classification number: H02M1/38 ,  H02M3/33561 ,  H02M3/33592 ,  Y02B70/1475

Abstract: A circuit for predicting the dead time is provided. The circuit includes a plurality of integrators, a plurality of comparators, and a logic circuit. Based on a reference signal provided externally, a first charging operation is delayed by a predetermined delay time during one period of the reference signal, such that the integrators maintain at a voltage level in a next period of the reference signal. Then, the integrators further perform another charging operation during the next period, and the charging voltage is compared with the maintained voltage value. When the charging voltage exceeds the maintained voltage, a reset signal is generated by the logic circuit.

Abstract translation: 提供了一种用于预测死区时间的电路。 电路包括多个积分器，多个比较器和逻辑电路。 基于外部提供的参考信号，在参考信号的一个周期期间，第一充电操作被延迟预定的延迟时间，使得积分器在参考信号的下一周期中保持在电压电平。 然后，积分器在下一个周期进一步进行另一个充电操作，并将充电电压与维持的电压值进行比较。 当充电电压超过维持电压时，由逻辑电路产生复位信号。

公开(公告)号：US06999050B2

公开(公告)日：2006-02-14

申请号：US10284250

申请日：2002-10-31

Applicant: Kun-Cheng Hung ,  Lin-Kai Bu

Inventor： Kun-Cheng Hung ,  Lin-Kai Bu

IPC: G09G3/36 ,  G09G3/28

CPC classification number: G09G3/3648 ,  G09G3/3614 ,  G09G2330/02 ,  G09G2330/023

Abstract: An apparatus for recycling energy in a liquid crystal display (LCD) so as to reduce energy loss when the LCD is driven by a driving circuit. The LCD includes two pixels, each of which has a corresponding capacitor and has a corresponding voltage applied to. The polarities of the voltages of the two corresponding capacitors are variable with time and are opposite to each other. The apparatus includes two switches and an energy converter. The two switches are used for selectively coupling the respective capacitors to the apparatus. The energy converter is used for outputting converted energy according to the voltages of the two capacitors. By enabling the first switch and the second switch selectively, the apparatus recycles energy dissipated during polarity inversion for the two pixels as energy for driving a load device.

Abstract translation: 一种用于在液晶显示器（LCD）中回收能量的装置，以便当LCD由驱动电路驱动时减少能量损失。 LCD包括两个像素，每个像素具有相应的电容器并具有施加的相应电压。 两个对应的电容器的电压的极性随时间变化并且彼此相反。 该装置包括两个开关和能量转换器。 两个开关用于将各个电容器选择性地耦合到该装置。 能量转换器用于根据两个电容器的电压输出转换的能量。 通过选择性地启用第一开关和第二开关，该装置回收在两个像素的极性反转期间消耗的能量作为用于驱动负载装置的能量。

公开(公告)号：USD436127S1

公开(公告)日：2001-01-09

申请号：US29125192

申请日：2000-06-20

Applicant: Kun-Cheng Hung

Designer： Kun-Cheng Hung

公开(公告)号：US07265697B2

公开(公告)日：2007-09-04

申请号：US11364725

申请日：2006-02-27

Applicant: Chin-Chung Tsai ,  Kun-Cheng Hung

Inventor： Chin-Chung Tsai ,  Kun-Cheng Hung

IPC: H03M1/66

CPC classification number: H01L27/0207 ,  H01L27/092 ,  H03M1/664 ,  H03M1/76

Abstract: In a decoder of a digital-to-analog converter, the gamma voltage selection is controlled by a reduced number of NMOS and PMOS transistors according to the characteristic of the NMOS and PMOS transistor, such that the layout area of the switch array is reduced. Moreover, a N-type buried diffusion (BDN) layer and a P-type buried diffusion (BDP) layer are adopted to replace the contacts in the layout of conventional decoder, such that the layout can be simplified and the bump pad pitch thereof can be decreased.

Abstract translation: 在数模转换器的解码器中，根据NMOS和PMOS晶体管的特性，通过减少数量的NMOS和PMOS晶体管控制伽马电压选择，使得开关阵列的布局面积减小。 此外，采用N型埋入扩散（BDN）层和P型埋入扩散（BDP）层来代替传统解码器布局中的触点，从而可以简化布局，并且其凸点焊盘间距可以 减少

公开(公告)号：US07123072B2

公开(公告)日：2006-10-17

申请号：US10128663

申请日：2002-04-23

Applicant: Linkai Bu ,  Chuan-Cheng Hsiao ,  Kun-Cheng Hung ,  Chien-Pin Chen

Inventor： Linkai Bu ,  Chuan-Cheng Hsiao ,  Kun-Cheng Hung ,  Chien-Pin Chen

IPC: G06G7/18

CPC classification number: H03M1/804

Abstract: A capacitor digital-to-analog converter for N-bit digital-to-analog conversion comprises a converter capacitor network comprising 2N capacitors and 2N+1 MOS switches and an output buffer. The MOS switches are connected in a series chain at their respective source/drain, and each of the capacitors has a first electrode connected to a corresponding joining node between two consecutive MOS switches in the series chain and a second electrode connected together to a common node. The output buffer comprises a differential amplifier and an output amplifier, the differential amplifier has 2N discrete inputs each connected to a corresponding one of the first electrodes of the capacitors in the converter capacitor network.

Abstract translation: 用于N位数模转换的电容器数模转换器包括一个包括2个N​​电容器和2个N + 1个MOS开关的转换器电容器网络，以及一个 输出缓冲区。 MOS开关在其各自的源极/漏极处以串联的方式连接，并且每个电容器具有连接到串联链中的两个连续的MOS开关之间的对应连接节点的第一电极和连接到公共节点的第二电极 。 输出缓冲器包括差分放大器和输出放大器，差分放大器具有两个离散输入端，每个离散输入端连接到转换器电容器网络中的电容器的对应的一个第一电极。

公开(公告)号：US20060114005A1

公开(公告)日：2006-06-01

申请号：US11117938

申请日：2005-04-28

Applicant: Shen-Yao Liang ,  Hung-Sung Chu ,  Kun-Cheng Hung

Inventor： Shen-Yao Liang ,  Hung-Sung Chu ,  Kun-Cheng Hung

IPC: G01R27/26

CPC classification number: H02M1/38 ,  H02M3/33561 ,  H02M3/33592 ,  Y02B70/1475

Abstract: A circuit for predicting the dead time is provided. The circuit comprises a plurality of integrators, a plurality of comparators, and a logic circuit. Based on a reference signal provided externally, a first charging operation is delayed by a predetermined delay time during one period of the reference signal, such that the integrators maintain at a voltage level in a next period of the reference signal. Then, the integrators further perform another charging operation during the next period, and the charging voltage is compared with the maintained voltage value. When the charging voltage exceeds the maintained voltage, a reset signal is generated by the logic circuit.

Abstract translation: 提供了一种用于预测死区时间的电路。 该电路包括多个积分器，多个比较器和逻辑电路。 基于外部提供的参考信号，在参考信号的一个周期期间，第一充电操作被延迟预定的延迟时间，使得积分器在参考信号的下一周期中保持在电压电平。 然后，积分器在下一个周期进一步进行另一个充电操作，并将充电电压与维持的电压值进行比较。 当充电电压超过维持电压时，由逻辑电路产生复位信号。

公开(公告)号：US06956554B2

公开(公告)日：2005-10-18

申请号：US10212077

申请日：2002-08-06

Applicant: Yen-Chen Chen ,  Chien-Pin Chen ,  Chuan-Cheng Hsiao ,  Lin-Kai Bu ,  Kun-Cheng Hung

Inventor： Yen-Chen Chen ,  Chien-Pin Chen ,  Chuan-Cheng Hsiao ,  Lin-Kai Bu ,  Kun-Cheng Hung

IPC: G09G3/36

CPC classification number: G09G3/3696 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2320/0276

Abstract: An apparatus for switching output voltage signals includes a resistor string, a first switching device set for delivering a number of gamma voltage input signals, a second switching device set for delivering a high voltage input signal and a low voltage input signal, and a switch selecting device coupled to the first switching device set and the second switching device set. When the switch selecting device outputs a first signal, the first switching device set can deliver the gamma voltage input signals to the resistor string; when the switch selecting device outputs a second signal, the second switching device set will deliver the high voltage input signal and the low voltage input signal to the resistor string.

Abstract translation: 用于切换输出电压信号的装置包括电阻串，用于传递多个伽马电压输入信号的第一开关装置，用于传送高电压输入信号和低电压输入信号的第二开关装置，以及开关选择 耦合到第一开关装置组和第二开关装置组的装置。 当开关选择装置输出第一信号时，第一开关装置可将伽马电压输入信号传送到电阻串; 当开关选择装置输出第二信号时，第二开关装置将高压输入信号和低电压输入信号传送到电阻串。