发明授权
US06812530B2 Methods for forming wordlines, transistor gates, and conductive interconnects, and wordline, transistor gate, and conductive interconnect structures
失效
用于形成字线，晶体管栅极和导电互连以及字线，晶体管栅极和导电互连结构的方法
- 专利标题： Methods for forming wordlines, transistor gates, and conductive interconnects, and wordline, transistor gate, and conductive interconnect structures
- 专利标题（中）： 用于形成字线，晶体管栅极和导电互连以及字线，晶体管栅极和导电互连结构的方法
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申请号： US09875501申请日： 2001-06-04
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公开(公告)号： US06812530B2公开(公告)日： 2004-11-02
- 发明人: Klaus Florian Schuegraf , Randhir P. S. Thakur
- 申请人： Klaus Florian Schuegraf , Randhir P. S. Thakur
- 主分类号： H01L2976
- IPC分类号： H01L2976
摘要：
The invention encompasses stacked semiconductor devices including gate stacks, wordlines, PROMs, conductive interconnecting lines, and methods for forming such structures. In one aspect, the invention includes a method of forming a conductive line comprising: a) forming a polysilicon layer; forming a silicide layer against the polysilicon layer; b) providing a conductivity-enhancing impurity within the silicide layer; and c) providing the polysilicon layer and the silicide layer into a conductive line shape. In another aspect, the invention includes a programmable-read-only-memory device comprising: a) a first dielectric layer over a substrate; b) a floating gate over the first dielectric layer; c) a second dielectric layer over the floating gate; d) a conductive line over the second dielectric layer; and e) a metal-silicide layer over the conductive line, the metal-silicide layer comprising a Group III dopant or a Group V dopant.
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