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1.发明授权公开(公告)号：US07067411B2
公开(公告)日：2006-06-27
申请号：US10789890
申请日：2004-02-27
IPC分类号： H01L21/4763
CPC分类号： H01L29/6656 , H01L21/28247 , H01L21/31683 , H01L21/32 , Y10S257/90
摘要： A selective spacer to prevent metal oxide formation during polycide reoxidation of a feature such as an electrode and a method for forming the selective spacer are disclosed. A material such as a thin silicon nitride or an amorphous silicon film is selectively deposited on the electrode by limiting deposition time to a period less than an incubation time for the material on silicon dioxide near the electrode. The spacer is deposited only on the electrode and not on surrounding silicon dioxide. The spacer serves as a barrier for the electrode during subsequent oxidation to prevent metal oxide formation while allowing oxidation to take place over the silicon dioxide.
摘要翻译： 公开了一种用于防止诸如电极的特征（例如电极）的聚合物再氧化期间的金属氧化物形成的选择性间隔物和用于形成选择性间隔物的方法。 将诸如薄氮化硅或非晶硅膜的材料通过将沉积时间限制在电极附近的二氧化硅上的材料的温育时间以下来选择性地沉积在电极上。 间隔物仅沉积在电极上而不是沉积在周围的二氧化硅上。 间隔物在随后的氧化期间用作电极的屏障，以防止金属氧化物形成，同时允许氧化发生在二氧化硅上。
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2.发明授权Method of forming a capacitor with two diffusion barrier layers formed in the same step 失效在同一步骤中形成具有两个扩散阻挡层的电容器的方法公开(公告)号：US06784052B2
公开(公告)日：2004-08-31
申请号：US10676498
申请日：2003-09-30
IPC分类号： H01L218242
CPC分类号： H01L21/7687 , H01L21/76843 , H01L21/76877 , H01L27/10852 , H01L27/10897 , H01L28/75 , H01L28/84
摘要： The invention includes: forming a capacitor electrode over one region of a substrate; forming a capacitor dielectric layer proximate the electrode; forming a conductive diffusion barrier layer, the conductive diffusion barrier layer being between the electrode and the capacitor dielectric layer; forming a conductive plug over another region of the substrate, the conductive plug comprising a same material as the conductive diffusion barrier layer; and at least a portion of the conductive plug being formed simultaneously with the conductive diffusion barrier layer.
摘要翻译： 本发明包括：在基板的一个区域上形成电容器电极; 在电极附近形成电容器电介质层; 形成导电扩散阻挡层，所述导电扩散阻挡层位于所述电极和所述电容器介电层之间; 在所述基板的另一区域上形成导电插塞，所述导电插塞包括与所述导电扩散阻挡层相同的材料; 并且所述导电插塞的至少一部分与所述导电扩散阻挡层同时形成。
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3.发明授权Capacitor constructions and semiconductor processing method of forming capacitor constructions 失效形成电容器结构的电容器结构和半导体加工方法
公开(公告)号：US5933723A
公开(公告)日：1999-08-03
申请号：US962483
申请日：1997-10-31
IPC分类号： H01L21/02 , H01L29/92 , H01L21/8234
CPC分类号： H01L28/40
摘要： A semiconductor processing method of forming a capacitor includes, a) providing a mass of electrically insulative oxide of a first density; b) densifying the oxide mass to a higher second density, the densified oxide mass being characterized by a wet etch rate of less than or equal to about 75 Angstroms/minute in a 100:1 by volume H.sub.2 O:HF solution; c) providing an electrically conductive inner capacitor plate over the underlying electrically insulative oxide layer and thereby defining an insulative layer and inner capacitor plate transition edge; d) after densifying the oxide mass, providing a capacitor dielectric layer over the inner capacitor plate and densified oxide mass, the capacitor dielectric layer comprising a nitride, the nitride containing capacitor dielectric layer having less thickness depletion at the transition edge than would otherwise occur were the oxide mass not subject to said densifying; and e) providing an electrically conductive outer capacitor plate over the capacitor dielectric layer. A capacitor construction includes, i) a dense mass of electrically insulative oxide; ii) an electrically conductive inner capacitor plate overlying and contacting the electrically insulative oxide mass; iii) a capacitor dielectric layer overlying the inner capacitor plate and oxide mass, the capacitor dielectric layer comprising a nitride; iv) an electrically conductive outer capacitor plate overlying the capacitor dielectric layer; and v) the dense mass of electrically insulative oxide contacting the inner capacitor plate being characterized by a wet etch rate of less than or equal to about 75 Angstroms/minute in a 100:1 by volume H.sub.2 O:HF solution.
摘要翻译： 形成电容器的半导体处理方法包括：a）提供第一密度的电绝缘氧化物的质量; b）将氧化物质量致密化为更高的第二密度，致密化的氧化物质量的特征在于在100:1体积比H 2 O：HF溶液中湿蚀刻速率小于或等于约75埃/分钟; c）在下面的电绝缘氧化物层上提供导电内部电容器板，从而限定绝缘层和内部电容器板过渡边缘; d）在致密化氧化物质量之后，在内部电容器板上形成电容器电介质层和致密的氧化物质量，电容器介电层包括氮化物，在过渡边缘处具有比否则将发生的具有较小厚度消耗的含氮化物的电容器电介质层是 氧化物质量不受所述致密化; 以及e）在所述电容器介电层上方提供导电的外部电容器板。 电容器结构包括：i）致密的电绝缘氧化物; ii）覆盖并接触电绝缘氧化物块的导电内电容器板; iii）覆盖内部电容器板和氧化物质的电容器电介质层，所述电容器介电层包括氮化物; iv）覆盖电容器介电层的导电外电容器板; 和v）接触内部电容器板的电绝缘氧化物的致密质量的特征在于在100:1体积比H 2 O：HF溶液中湿蚀刻速率小于或等于约75埃/分钟。
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4.发明授权Selective spacer to prevent metal oxide formation during polycide reoxidation 失效选择性间隔物，以防止在多偶氮化物再氧化过程中形成金属氧化物公开(公告)号：US07009264B1
公开(公告)日：2006-03-07
申请号：US08902809
申请日：1997-07-30
IPC分类号： H01L29/76
CPC分类号： H01L29/6656 , H01L21/28247 , H01L21/31683 , H01L21/32 , Y10S257/90
摘要： A selective spacer to prevent metal oxide formation during polycide reoxidation of a feature such as an electrode and a method for forming the selective spacer are disclosed. A material such as a thin silicon nitride or an amorphous silicon film is selectively deposited on the electrode by limiting deposition time to a period less than an incubation time for the material on silicon dioxide near the electrode. The spacer is deposited only on the electrode and not on surrounding silicon dioxide. The spacer serves as a barrier for the electrode during subsequent oxidation to prevent metal oxide formation while allowing oxidation to take place over the silicon dioxide.
摘要翻译： 公开了一种用于防止诸如电极的特征（例如电极）的聚合物再氧化期间的金属氧化物形成的选择性间隔物和用于形成选择性间隔物的方法。 将诸如薄氮化硅或非晶硅膜的材料通过将沉积时间限制在电极附近的二氧化硅上的材料的温育时间以下来选择性地沉积在电极上。 间隔物仅沉积在电极上而不是沉积在周围的二氧化硅上。 间隔物在随后的氧化期间用作电极的屏障，以防止金属氧化物形成，同时允许氧化发生在二氧化硅上。
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5.发明授权Methods for forming wordlines, transistor gates, and conductive interconnects, and wordline, transistor gate, and conductive interconnect structures 有权用于形成字线，晶体管栅极和导电互连以及字线，晶体管栅极和导电互连结构的方法公开(公告)号：US06611032B2
公开(公告)日：2003-08-26
申请号：US09879742
申请日：2001-06-11
IPC分类号： H01L2976
CPC分类号： H01L29/4941 , H01L21/28061 , H01L21/28273 , H01L29/4916
摘要： The invention encompasses stacked semiconductor devices including gate stacks, wordlines, PROMs, conductive interconnecting lines, and methods for forming such structures. The invention also includes a method of forming a transistor gate comprising: a) forming gate dielectric layer; b) forming a polysilicon gate layer against the gate dielectric layer; and c) doping the polysilicon gate layer with a conductivity-enhancing dopant, the dopant being provided in a concentration gradient within the polysilicon layer, the concentration gradient increasing in a direction toward the gate dielectric layer. The invention also includes a wordline comprising: a) a polysilicon line; a substantially fluorine impervious barrier layer over the polysilicon line; and a b) layer of metal-silicide over the substantially fluorine impervious barrier layer.
摘要翻译： 本发明包括堆叠的半导体器件，包括栅极堆叠，字线，PROM，导电互连线以及用于形成这种结构的方法。 本发明还包括一种形成晶体管栅极的方法，包括：a）形成栅极介电层; b）在所述栅极介电层上形成多晶硅栅极层; 以及c）用导电性增强掺杂剂掺杂多晶硅栅极层，所述掺杂剂以所述多晶硅层内的浓度梯度提供，所述浓度梯度在朝向所述栅极介电层的方向上增加。 本发明还包括字线，包括：a）多晶硅线; 多晶硅线上的基本上不透氟的阻挡层; 以及b）基本上不透氟化阻挡层上的金属硅化物层。
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公开(公告)号：US06355549B1
公开(公告)日：2002-03-12
申请号：US09688259
申请日：2000-10-13
IPC分类号： H01L213205
CPC分类号： H01L29/66583 , H01L21/28052 , H01L21/28123 , H01L21/32053 , H01L21/76895
摘要： A method of forming a polycide structure in accordance with the present invention includes forming a polysilicon layer on a surface. A refractory metal silicide portion of the polycide structure is formed on the polysilicon layer and the polysilicon portion of the polycide line is formed after formation of the metal silicide portion. The formation of the metal silicide portion of the polycide structure may include forming an oxide hard mask over the polysilicon layer exposing line portions of the polysilicon layer. The exposed line portions of the polysilicon layer are silicided resulting in a refractory metal silicide portion and unreacted material over the oxide hard mask. The unreacted material and oxide hard mask are then removed. The refractory metal silicide portion may be formed by forming a refractory metal or metal silicide layer, such as cobalt or cobalt silicide, over the oxide hard mask and exposed portions of the polysilicon layer. The refractory metal or metal silicide layer is then reacted with the polysilicon layer resulting in the refractory metal silicide portion of the polycide structure. Another method includes forming a polycide structure by using a refractory metal silicide portion of the polycide structure as a hard mask to remove portions of an underlying layer of polysilicon to form the polysilicon portion of the polycide structure. The polycide structure may be a polycide bit line, word line, interconnect or any other polycide structure.
摘要翻译： 根据本发明的形成多晶硅结构的方法包括在表面上形成多晶硅层。 在多晶硅层上形成多晶硅结构的难熔金属硅化物部分，并且在形成金属硅化物部分之后形成多晶硅化物线的多晶硅部分。 多晶硅化物结构的金属硅化物部分的形成可以包括在暴露多晶硅层的线路部分的多晶硅层上形成氧化物硬掩模。 多晶硅层的暴露的线部分被硅化，导致难熔金属硅化物部分和氧化物硬掩模上的未反应材料。 然后除去未反应的材料和氧化物硬掩模。 难熔金属硅化物部分可以通过在氧化物硬掩模和多晶硅层的暴露部分上形成难熔金属或金属硅化物层（例如钴或钴硅化物）来形成。 然后使难熔金属或金属硅化物层与多晶硅层反应，得到多晶硅化物结构的难熔金属硅化物部分。 另一种方法包括通过使用多晶硅结构的难熔金属硅化物部分作为硬掩模来形成多晶硅结构，以去除多晶硅的下层的部分以形成多晶硅结构的多晶硅部分。 多晶硅化合物结构可以是多晶硅位线，字线，互连或任何其它聚硅氧烷结构。
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公开(公告)号：US6165838A
公开(公告)日：2000-12-26
申请号：US83595
申请日：1998-05-22
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L28/40
摘要： A capacitor and a method for forming a capacitor is described and which includes providing a node location to which electrical connection to a capacitor is to be made; providing an amorphous inner capacitor plate layer of a first material atop the node location; providing a capacitor dielectric layer outwardly of the first material; after providing the capacitor dielectric layer, rendering the first material to be polycrystalline; providing an electrically conductive outer capacitor plate layer outwardly of the capacitor dielectric layer; and providing the first material to be electrically conductive. The capacitor formed by the present method exhibits current leakage characteristics which are substantially symmetrical with respect to both positive and negative voltage bias and characterized by differences between the positive and negative voltage bias being within less than about 10 percent for a predetermined voltage.
摘要翻译： 描述了用于形成电容器的电容器和方法，其中包括提供与电容器进行电连接的节点位置; 在所述节点位置的顶部提供第一材料的非晶内电容器板层; 在所述第一材料的外部提供电容器电介质层; 在提供电容器介电层之后，使第一材料变为多晶; 在所述电容器介电层的外部提供导电外电容器板层; 并提供第一材料以导电。 通过本方法形成的电容器具有相对于正电压偏置和负电压偏置基本对称的电流泄漏特性，其特征在于正电压偏置和负电压偏差之间的差异在预定电压的小于约10％内。
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公开(公告)号：US06548852B2
公开(公告)日：2003-04-15
申请号：US09797900
申请日：2001-03-01
IPC分类号： H01L27108
CPC分类号： H01L21/7687 , H01L21/76843 , H01L21/76877 , H01L27/10852 , H01L27/10897 , H01L28/75 , H01L28/84
摘要： In one aspect, the invention includes a method of forming circuitry comprising: a) forming a capacitor electrode over one region of a substrate: b) forming a capacitor dielectric layer proximate the electrode; c) forming a conductive diffusion barrier layer, the conductive diffusion barrier layer being between the electrode and the capacitor dielectric layer; d) forming a conductive plug over another region of the substrate, the conductive plug comprising a same material as the conductive diffusion barrier layer; and e) at least a portion of the conductive plug being formed simultaneously with the conductive diffusion barrier layer. In another aspect, the invention includes an integrated circuit comprising a capacitor and a conductive plug, the conductive plug and capacitor comprising a first common and continuous layer. In yet another aspect, the invention includes a circuit construction comprising: a) a substrate having a memory array region and a peripheral region that is peripheral to the memory array region; b) a capacitor construction over the memory array region of the substrate, the capacitor construction comprising a storage node, a capacitor dielectric layer and a cell plate layer; the capacitor dielectric layer being between the storage node and the cell plate layer; and c) an electrical interconnect over the peripheral region, the interconnect being electrically connected to the cell plate layer and extending between the cell plate layer and the substrate.
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公开(公告)号：US06303965B1
公开(公告)日：2001-10-16
申请号：US09378434
申请日：1999-08-20
IPC分类号： H01L2976
CPC分类号： H01L28/20 , H01L27/11 , H01L27/1112 , Y10S257/903 , Y10S257/904
摘要： The invention encompasses resistors comprising a thin layer of dielectric material and methods of forming such resistors. The invention also encompasses integrated circuitry comprising such resistors, including SRAM circuitry, and encompasses methods of forming such integrated circuitry. In one aspect, the invention includes a resistor construction for electrically connecting a first node location to a second node location comprising: a) a first conductive layer in electrical connection with the first node location; b) a second conductive layer in electrical connection with the second node location; and c) a dielectric material intermediate the first conductive layer and the second conductive layer and having a thickness of from about 15 Angstroms to about 60 Angstroms. In another aspect, the invention includes a resistor construction for electrically connecting a first node location to a second node location comprising: a) a dielectric material in electrical connection with the first node location and having a thickness of no greater than about 60 Angstroms; and b) a conductive layer over the dielectric material and in electrical connection with the second node location.
摘要翻译： 本发明包括包括介电材料薄层的电阻器和形成这种电阻器的方法。 本发明还包括包括这样的电阻器的集成电路，包括SRAM电路，并且包括形成这种集成电路的方法。 一方面，本发明包括用于将第一节点位置电连接到第二节点位置的电阻器结构，包括：a）与第一节点位置电连接的第一导电层; b）与第二节点位置电连接的第二导电层; 以及c）介于第一导电层和第二导电层之间的电介质材料，其厚度为约15埃至约60埃。 在另一方面，本发明包括用于将第一节点位置电连接到第二节点位置的电阻器结构，包括：a）与第一节点位置电连接且具有不大于约60埃的厚度的电介质材料; 以及b）介电材料上方并与第二节点位置电连接的导电层。
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公开(公告)号：US6156632A
公开(公告)日：2000-12-05
申请号：US911840
申请日：1997-08-15
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/768 , H01L21/4763
CPC分类号： H01L29/66583 , H01L21/28052 , H01L21/28123 , H01L21/32053 , H01L21/76895
摘要： A method of forming a polycide structure in accordance with the present invention includes forming a polysilicon layer on a surface. A refractory metal silicide portion of the polycide structure is formed on the polysilicon layer and the polysilicon portion of the polycide line is formed after formation of the metal siticide portion. The formation of the metal silicide portion of the polycide structure may include forming an oxide hard mask over the polysilicon layer exposing line portions of the polysilicon layer. The exposed line portions of the polysilicon layer are silicided resulting in a refractory metal silicide portion and unreacted material over the oxide hard mask. The unreacted material and oxide hard mask are then removed. The refractory metal silicide portion may be formed by forming a refractory metal or metal silicide layer, such as cobalt or cobalt silicide, over the oxide hard mask and exposed portions of the polysilicon layer. The refractory metal or metal silicide layer is then reacted with the polysilicon layer resulting in the refractory meal silicide portion of the polycide structure. Another method includes forming a polycide structure by using a refractory metal silicide portion of the polycide structure as a hard mask to remove portions of an underlying layer of polysilicon to form the polysilicon portion of the polycide structure. The polycide structure may be a polycide bit line, word line, interconnect or any other polycide structure.
摘要翻译： 根据本发明的形成多晶硅结构的方法包括在表面上形成多晶硅层。 在多晶硅层上形成多晶硅结构的难熔金属硅化物部分，并且在形成金属硅化物部分之后形成多晶硅化物线的多晶硅部分。 多晶硅化物结构的金属硅化物部分的形成可以包括在暴露多晶硅层的线路部分的多晶硅层上形成氧化物硬掩模。 多晶硅层的暴露的线部分被硅化，导致难熔金属硅化物部分和氧化物硬掩模上的未反应材料。 然后除去未反应的材料和氧化物硬掩模。 难熔金属硅化物部分可以通过在氧化物硬掩模和多晶硅层的暴露部分上形成难熔金属或金属硅化物层（例如钴或钴硅化物）来形成。 然后使难熔金属或金属硅化物层与多晶硅层反应，导致多晶硅结构的耐火膳食硅化物部分。 另一种方法包括通过使用多晶硅结构的难熔金属硅化物部分作为硬掩模来形成多晶硅结构，以去除多晶硅的下层的部分以形成多晶硅结构的多晶硅部分。 多晶硅化合物结构可以是多晶硅位线，字线，互连或任何其它聚硅氧烷结构。
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