发明授权
US06816429B2 Integrated circuit capable of being burn-in tested using an alternating current stress and a testing method using the same
有权
能够使用交流电压进行老化测试的集成电路和使用该电路的测试方法
- 专利标题: Integrated circuit capable of being burn-in tested using an alternating current stress and a testing method using the same
- 专利标题(中): 能够使用交流电压进行老化测试的集成电路和使用该电路的测试方法
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申请号: US10268380申请日: 2002-10-09
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公开(公告)号: US06816429B2公开(公告)日: 2004-11-09
- 发明人: Sang-jib Han , Du-eung Kim , Choong-keun Kwak , Yun-seung Shin
- 申请人: Sang-jib Han , Du-eung Kim , Choong-keun Kwak , Yun-seung Shin
- 优先权: KR99-27991 19990712
- 主分类号: G11C700
- IPC分类号: G11C700
摘要:
An integrated circuit that is capable of being burn-in tested with an AC stress and a testing method using the same are provided. The integrated circuit includes an address transforming means and a data generating means. The address transforming means transforms the addresses of the memory device selected and generates an address signal responsive to a clock signal. The data generating means generates a data signal that alternates between a first state and a second state responsive to the clock signal and provides the data signal to the selected memory device. The integrated circuit includes a switch for coupling the test supply line to the normal supply line during testing and intercepting the test supply line from the normal supply line during normal operations responsive to a control signal. The integrated circuit of the present invention allows a wafer burn-in test by sequentially and repeatedly applying the AC stress to all the memory devices.
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