公开(公告)号：US06816429B2

公开(公告)日：2004-11-09

申请号：US10268380

申请日：2002-10-09

申请人： Sang-jib Han ,  Du-eung Kim ,  Choong-keun Kwak ,  Yun-seung Shin

发明人： Sang-jib Han ,  Du-eung Kim ,  Choong-keun Kwak ,  Yun-seung Shin

IPC分类号： G11C700

CPC分类号： G11C29/50

摘要： An integrated circuit that is capable of being burn-in tested with an AC stress and a testing method using the same are provided. The integrated circuit includes an address transforming means and a data generating means. The address transforming means transforms the addresses of the memory device selected and generates an address signal responsive to a clock signal. The data generating means generates a data signal that alternates between a first state and a second state responsive to the clock signal and provides the data signal to the selected memory device. The integrated circuit includes a switch for coupling the test supply line to the normal supply line during testing and intercepting the test supply line from the normal supply line during normal operations responsive to a control signal. The integrated circuit of the present invention allows a wafer burn-in test by sequentially and repeatedly applying the AC stress to all the memory devices.

摘要翻译： 提供了能够用AC应力进行老化测试的集成电路和使用其的测试方法。 集成电路包括地址转换装置和数据产生装置。 地址变换装置变换选择的存储器件的地址，并响应于时钟信号产生地址信号。 数据产生装置产生响应于时钟信号在第一状态和第二状态之间交替的数据信号，并将数据信号提供给选择的存储器件。 集成电路包括用于在测试期间将测试电源线连接到正常供电线的开关，并且响应于控制信号在正常操作期间从正常供电线截取测试电源线。 本发明的集成电路允许通过对所有的存储器件顺序并重复地施加AC应力来进行晶片老化测试。

公开(公告)号：US06490223B1

公开(公告)日：2002-12-03

申请号：US09614783

申请日：2000-07-12

申请人： Sang-jib Han ,  Du-eung Kim ,  Choong-keun Kwak ,  Yun-seung Shin

发明人： Sang-jib Han ,  Du-eung Kim ,  Choong-keun Kwak ,  Yun-seung Shin

IPC分类号： G11C800

CPC分类号： G11C29/50

摘要： An integrated circuit that is capable of being burn-in tested with an AC stress and a testing method using the same are provided. The integrated circuit includes an address transforming means and a data generating means. The address transforming means transforms the addresses of the memory cell selected and generates an address signal responsive to a clock signal. The data generating means generates a data signal that alternates between a first state and a second state responsive to the clock signal and provides the data signal to the selected memory cell. The integrated circuit includes a switch for coupling the test supply line to the normal supply line during testing and intercepting the test supply line from the normal supply line during normal operations responsive to a control signal. The integrated circuit of the present invention allows a wafer burn-in test by sequentially and repeatedly applying the AC stress to all the memory cells.

摘要翻译： 提供了能够用AC应力进行老化测试的集成电路和使用其的测试方法。 集成电路包括地址转换装置和数据产生装置。 地址变换装置对所选存储单元的地址进行变换，并根据时钟信号生成地址信号。 数据产生装置产生响应于时钟信号在第一状态和第二状态之间交替的数据信号，并将数据信号提供给选定的存储单元。 集成电路包括用于在测试期间将测试电源线连接到正常供电线的开关，并且响应于控制信号在正常操作期间从正常供电线截取测试电源线。 本发明的集成电路允许通过对所有的存储单元顺序并重复地施加AC应力来进行晶片老化测试。

公开(公告)号：US07573411B2

公开(公告)日：2009-08-11

申请号：US12007333

申请日：2008-01-09

申请人： Yun-seung Shin ,  Ju-hyun Ko

发明人： Yun-seung Shin ,  Ju-hyun Ko

IPC分类号： H03M1/68 ,  G09G5/10

CPC分类号： H03M1/667 ,  H03M1/662 ,  H03M1/682 ,  H03M1/765

摘要： A digital-to-analog converter outputting an analog data voltage corresponding to n-bit data, includes a chopping amplification unit adapted to receive an upper bit voltage corresponding to upper x bits of the n-bit data and a lower bit voltage corresponding to lower y bits of the n-bit data and to output the analog data voltage. The chopping amplification unit may include a sample and hold capacitor adapted to be charged with the upper bit voltage in a non-inverting mode, and a chopping amplifier adapted to supply the upper bit voltage to the sample and hold capacitor in the non-inverting mode and adapted to output a voltage corresponding to the sum of the upper bit voltage and the lower bit voltage as the analog data voltage in an inverting mode.

摘要翻译： 输出对应于n位数据的模拟数据电压的数模转换器包括斩波放大单元，其适于接收对应于n位数据的高x位的高位电压和对应于低位的低位电压 y比特数据，并输出模拟数据电压。 斩波放大单元可以包括适于以非反相模式对高位电压进行充电的采样和保持电容器，以及斩波放大器，其适于以非反相模式将采样和保持电容器提供高位电压 并且适于在反相模式中输出对应于高位电压和低位电压之和的电压作为模拟数据电压。

公开(公告)号：US20080074917A1

公开(公告)日：2008-03-27

申请号：US11902711

申请日：2007-09-25

申请人： Woo-yeong Cho ,  Yun-seung Shin

发明人： Woo-yeong Cho ,  Yun-seung Shin

IPC分类号： G11C11/02

CPC分类号： G11C11/1675 ,  G11C11/1655 ,  G11C11/1659 ,  Y10S977/935

摘要： A magnetoresistive random access memory (RAM) may include a plurality of variable resistance devices, a plurality of read bitlines electrically connected to respective variable resistance devices, and a plurality of write bitlines alternating with the read bitlines. The magnetoresistive RAM may be configured to apply a first write current through a first write bitline adjacent to a first variable resistance device when writing a first data to the first variable resistance device, and apply a first inhibition current through a second write bitline adjacent to a second variable resistance device, the second variable resistance device being adjacent to the first write bitline, and between the first write bitline and the second write bitline, and the first write current and the first inhibition current flowing in a same direction.

摘要翻译： 磁阻随机存取存储器（RAM）可以包括多个可变电阻器件，电连接到相应的可变电阻器件的多个读位线以及与读位线交替的多个写位线。 磁阻RAM可以被配置为当向第一可变电阻器件写入第一数据时，通过与第一可变电阻器件相邻的第一写入位线施加第一写入电流，并且将第一写入电流施加到与第一可写入位置相邻的第二写入位置 第二可变电阻器件，第二可变电阻器件与第一写入位线相邻，第一写入位线和第二写入位线之间以及第一写入电流和第一抑制电流沿相同的方向流动。

公开(公告)号：US5965939A

公开(公告)日：1999-10-12

申请号：US838044

申请日：1997-04-22

申请人： Kyeong-tae Kim ,  Yun-seung Shin ,  Young-hun Park ,  Won-mo Park ,  Ji-hong Ahn

发明人： Kyeong-tae Kim ,  Yun-seung Shin ,  Young-hun Park ,  Won-mo Park ,  Ji-hong Ahn

IPC分类号： H01L21/3205 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L23/48

CPC分类号： H01L27/10808 ,  H01L21/31056 ,  H01L21/76819 ,  H01L27/105 ,  Y10S438/926

摘要： A semiconductor device having a closed step portion and a global step portion including an insulating layer having a planarized surface on the global step portion is provided. A dummy pattern is formed by forming an insulating layer on the global step portion and then patterning through a photolithography process. After forming the dummy pattern for compensating steps in the global step portion and between the closed step portion and the global step portion, a BPSG layer is formed on both the closed step portion and the global step portion, and then the BPSG layer is heat-treated to cause it to reflow. The BPSG layer as an insulating interlayer having a planarized surface. The improved planarization decreases the occurrence of notching and discontinuities in the succeeding metallization processes thereby enhancing the yield and electrical characteristics of the semiconductor device.

摘要翻译： 提供一种半导体器件，其具有闭合台阶部分和包括在全局台阶部分上具有平坦化表面的绝缘层的全局阶跃部分。 通过在全局台阶部分上形成绝缘层，然后通过光刻工艺进行图案化，形成虚拟图案。 在形成用于补偿全局台阶部分之间和闭合台阶部分与全局台阶部分之间的步骤的虚拟图案之后，在封闭台阶部分和全局台阶部分上形成BPSG层，然后BPSG层被热封， 处理以使其回流。 作为具有平坦化表面的绝缘中间层的BPSG层。 改进的平面化减少了随后的金属化处理中的开槽和不连续的发生，从而提高了半导体器件的产量和电特性。

公开(公告)号：US07952918B2

公开(公告)日：2011-05-31

申请号：US12875297

申请日：2010-09-03

申请人： Woo-yeong Cho ,  Yun-seung Shin

发明人： Woo-yeong Cho ,  Yun-seung Shin

IPC分类号： G11C11/00

CPC分类号： G11C11/1675 ,  G11C11/1655 ,  G11C11/1659 ,  Y10S977/935

摘要： A magnetoresistive random access memory (RAM) may include a plurality of variable resistance devices, a plurality of read bitlines electrically connected to respective variable resistance devices, and a plurality of write bitlines alternating with the read bitlines. The magnetoresistive RAM may be configured to apply a first write current through a first write bitline adjacent to a first variable resistance device when writing a first data to the first variable resistance device, and apply a first inhibition current through a second write bitline adjacent to a second variable resistance device, the second variable resistance device being adjacent to the first write bitline, and between the first write bitline and the second write bitline, and the first write current and the first inhibition current flowing in a same direction.

摘要翻译： 磁阻随机存取存储器（RAM）可以包括多个可变电阻器件，电连接到相应的可变电阻器件的多个读位线以及与读位线交替的多个写位线。 磁阻RAM可以被配置为当向第一可变电阻器件写入第一数据时，通过与第一可变电阻器件相邻的第一写入位线施加第一写入电流，并且将第一写入电流施加到与第一可写入位置相邻的第二写入位置 第二可变电阻器件，第二可变电阻器件与第一写入位线相邻，第一写入位线和第二写入位线之间以及第一写入电流和第一抑制电流沿相同的方向流动。

公开(公告)号：US5858860A

公开(公告)日：1999-01-12

申请号：US795103

申请日：1997-02-06

申请人： Myoung-seob Shim ,  Won-taek Choi ,  Yun-seung Shin

发明人： Myoung-seob Shim ,  Won-taek Choi ,  Yun-seung Shin

IPC分类号： H01L21/316 ,  H01L21/76 ,  H01L21/762

CPC分类号： H01L21/76202 ,  Y10S438/978

摘要： Isolated semiconductor devices are formed by forming field oxide regions in a face of a semiconductor substrate to define active regions therebetween. The field oxide regions extend to above the substrate face and include an oblique surface which extends from above the substrate face to the substrate face. A step reducing region is formed on a respective one of the oblique surfaces of the field oxide regions, extending onto the active regions at the substrate face. The step reducing region can reduce the steepness of the step between the substrate face and the field oxide regions, thereby facilitating further processing and reliability of the semiconductor devices.

摘要翻译： 隔离半导体器件通过在半导体衬底的表面形成场氧化物区域以在其间限定有效区域来形成。 场氧化物区域延伸到衬底面的上方，并且包括从衬底表面上方延伸到衬底面的倾斜表面。 在场氧化物区域的相应一个倾斜表面上形成有延伸到衬底面上的有源区上的阶梯减小区域。 减小栅极区域可以降低衬底面和场氧化物区域之间的台阶的陡度，从而有助于半导体器件的进一步处理和可靠性。

公开(公告)号：US5523255A

公开(公告)日：1996-06-04

申请号：US455646

申请日：1995-05-31

申请人： Yong-woo Hyung ,  Don-young Ku ,  Byung-hong Chung ,  Yong-oon Hwang ,  Hung-mo Yang ,  Yun-seung Shin

发明人： Yong-woo Hyung ,  Don-young Ku ,  Byung-hong Chung ,  Yong-oon Hwang ,  Hung-mo Yang ,  Yun-seung Shin

IPC分类号： H01L21/316 ,  H01L21/318 ,  H01L21/32 ,  H01L21/76

CPC分类号： H01L21/32 ,  Y10S438/911

摘要： A method for forming a device isolation film of a semiconductor device, which includes the steps of forming a pad oxide film on a semiconductor substrate, forming an oxidation buffer layer on the pad oxide film, forming an oxidation prevention film on the oxidation buffer layer, forming an aperture in the oxidation prevention film and a longitudinally co-extensive recess in the oxidation buffer layer, to thereby expose a portion of the oxidation buffer layer, forming a cap oxide film on the exposed portion of the oxidation buffer layer by subjecting a first resultant structure obtained by the preceding steps to a thermal oxidation process, forming an oxynitride film at an interface between the cap oxide film and the oxidation buffer layer by heat-treating a second resultant structure obtained by the preceding steps in a nitrogen atmosphere, and, forming the device isolation film by subjecting a third resultant structure obtained by the preceding steps to a thermal oxidation process.

摘要翻译： 一种形成半导体器件的器件隔离膜的方法，包括以下步骤：在半导体衬底上形成衬垫氧化膜，在衬垫氧化膜上形成氧化缓冲层，在氧化缓冲层上形成氧化防止膜， 在氧化防止膜中形成孔，在氧化缓冲层中形成纵向共同延伸的凹部，从而暴露出氧化缓冲层的一部分，在氧化缓冲层的暴露部分上形成帽氧化膜， 通过前述步骤获得的热成型结构，通过在氮气气氛中热处理由前述步骤获得的第二结果结构，在盖氧化膜和氧化缓冲层之间的界面处形成氧氮化物膜， 通过将由前述步骤获得的第三结果结构进行热氧化处理来形成器件隔离膜。

公开(公告)号：US5488007A

公开(公告)日：1996-01-30

申请号：US42490

申请日：1993-04-16

申请人： Kyeong-Tae Kim ,  Yun-seung Shin ,  Young-hun Park ,  Won-mo Park ,  Ji-hong Ahn

发明人： Kyeong-Tae Kim ,  Yun-seung Shin ,  Young-hun Park ,  Won-mo Park ,  Ji-hong Ahn

IPC分类号： H01L21/3205 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L21/00

CPC分类号： H01L27/10808 ,  H01L21/31056 ,  H01L21/76819 ,  H01L27/105 ,  Y10S438/926

摘要： A method for manufacturing a semiconductor device having a closed step portion and a global step portion including an insulating layer is provided. A dummy pattern is formed by forming an insulating layer on the global step portion and then patterning through a photolithography process. After forming the dummy pattern for compensating steps in the global step portion and between the closed step portion and the global step portion, a BPSG layer is formed on both the closed step portion and the global step portion, and then the BPSG layer is heat-treated to cause it to reflow. The BPSG layer as an insulating interlayer having a planarized surface. The improved planarization decreases the occurrence of notching and discontinuities in the succeeding metallization processes thereby enhancing the yield and electrical characteristics of the semiconductor device.

摘要翻译： 提供了一种制造具有封闭台阶部分和包括绝缘层的全局台阶部分的半导体器件的方法。 通过在全局台阶部分上形成绝缘层，然后通过光刻工艺进行图案化，形成虚拟图案。 在形成用于补偿全局台阶部分之间和闭合台阶部分与全局台阶部分之间的步骤的虚拟图案之后，在封闭台阶部分和全局台阶部分上形成BPSG层，然后BPSG层被热封， 处理以使其回流。 作为具有平坦化表面的绝缘中间层的BPSG层。 改进的平面化减少了随后的金属化处理中的开槽和不连续的发生，从而提高了半导体器件的产量和电特性。

公开(公告)号：US5960293A

公开(公告)日：1999-09-28

申请号：US806080

申请日：1997-02-25

申请人： Weon-cheol Hong ,  Yun-seung Shin

发明人： Weon-cheol Hong ,  Yun-seung Shin

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： A method for forming a capacitor for an integrated circuit device includes the following steps. An interlayer dielectric layer is formed on a substrate, and a contact hole is formed in the interlayer dielectric layer. A first conductive layer is then formed on the interlayer dielectric layer, wherein the first conductive layer is electrically connected to the substrate through the contact hole. A hole having a depth less than the thickness of the first conductive layer is etched in the first conductive layer. An insulating layer is formed in the hole and the first conductive layer is then etched to a predetermined depth using the insulating layer as an etching mask to expose a side wall of an upper portion of the insulating layer. A spacer is formed on the side wall of the upper portion of the insulating layer. The first conductive layer is then etched using the insulating layer and the spacer as etching marks to form an electrode structure. The insulating layer and spacer are then removed. Lastly, the capacitor is completed by forming a dielectric layer on the electrode structure and then forming a second conductive layer on the dielectric layer.

摘要翻译： 一种用于形成用于集成电路器件的电容器的方法包括以下步骤。 在基板上形成层间电介质层，在层间电介质层中形成接触孔。 然后在层间电介质层上形成第一导电层，其中第一导电层通过接触孔与基板电连接。 在第一导电层中蚀刻深度小于第一导电层的厚度的孔。 在孔中形成绝缘层，然后使用绝缘层作为蚀刻掩模将第一导电层蚀刻到预定深度，以暴露绝缘层的上部的侧壁。 在绝缘层的上部的侧壁上形成间隔物。 然后使用绝缘层和间隔物作为蚀刻标记来蚀刻第一导电层以形成电极结构。 然后去除绝缘层和间隔物。 最后，通过在电极结构上形成电介质层，然后在电介质层上形成第二导电层来完成电容器。