A micro-controller direct memory access (DMA) unit includes hardware support for single read of the source address at a source word size and but writes to the target address at an independent target word size. This permits, for example, a single read of the source address at a larger word size and multiple sub-word sized writes to the target address. This is enabled by independent control register storage of a source word size, a source increment size, a target word size and a target increment size. A byte shifter/register that will shifts a full byte at a time to the next lower byte position allowing transfer of a large word to a destination having a small word size.