公开(公告)号：US06829669B2

公开(公告)日：2004-12-07

申请号：US09932377

申请日：2001-08-17

申请人： Steven R. Jahnke ,  Hiromichi Hamakawa

发明人： Steven R. Jahnke ,  Hiromichi Hamakawa

IPC分类号： G06F1336

CPC分类号： G06F13/4059 ,  G06F13/4031

摘要： A bus bridge is defined to provide an interface between two AHB buses. These busses normally have separate requirements but both must provide high performance. The first is for transfer of data from CPU to memory and peripherals. The second is to support the transfer of a large amount of data by a single peripheral to local memory or other local peripherals. The AHB-to-HTB bus bridge provides a means for the interfacing these two separate AHB buses allowing communication between them and securing data integrity. The bus bridge of this invention is defined to be an AHB memory bus slave but a high performance data transfer bus master.

摘要翻译： 一个总线桥被定义为提供两条AHB总线之间的接口。 这些总线通常具有单独的要求，但两者都必须提供高性能。 第一个是将数据从CPU传输到内存和外围设备。 第二个是支持通过单个外设向本地存储器或其他本地外围设备传输大量数据。 AHB到HTB总线桥提供了一种用于连接这两个单独的AHB总线的手段，从而允许它们之间的通信并保证数据的完整性。 本发明的总线桥被定义为AHB存储器总线从机，而是高性能数据传输总线主机。

公开(公告)号：US06816921B2

公开(公告)日：2004-11-09

申请号：US09932135

申请日：2001-08-17

申请人： Steven R. Jahnke ,  Hiromichi Hamakawa

发明人： Steven R. Jahnke ,  Hiromichi Hamakawa

IPC分类号： G06F1322

CPC分类号： G06F13/28

摘要： A micro-controller direct memory access (DMA) unit includes hardware support for single read of the source address at a source word size and but writes to the target address at an independent target word size. This permits, for example, a single read of the source address at a larger word size and multiple sub-word sized writes to the target address. This is enabled by independent control register storage of a source word size, a source increment size, a target word size and a target increment size. A byte shifter/register that will shifts a full byte at a time to the next lower byte position allowing transfer of a large word to a destination having a small word size.

摘要翻译： 微控制器直接存储器访问（DMA）单元包括对来源字大小的源地址的单次读取的硬件支持，并且以独立的目标字大小写入目标地址。 这允许例如以更大的字大小和对目标地址的多个子字大小的写入对源地址的单次读取。 这通过源字大小，源增量大小，目标字大小和目标增量大小的独立控制寄存器存储来实现。 一个字节移位器/寄存器，将一次将全字节移位到下一个较低字节位置，允许将一个大字转移到具有较小字大小的目的地。

公开(公告)号：US06775732B2

公开(公告)日：2004-08-10

申请号：US09932584

申请日：2001-08-17

申请人： Steven R. Jahnke ,  Hiromichi Hamakawa

发明人： Steven R. Jahnke ,  Hiromichi Hamakawa

IPC分类号： G06F1300

CPC分类号： G06F13/4031

摘要： This invention comprises a multiple transaction advanced high performance bus AHB system using two separate fully autonomous AHB buses, each having its own bus arbitration system with decoding to allow for simultaneous activity on the two AHB buses. The two buses are separated by and synchronized with an AHB-to-HTB bus bridge. The first bus, the Memory Bus AHB, contains the CPU and DMA as bus masters and the external memory controller and internal memory as slaves. The second bus, the Data Transfer Bus HTB, contains the high performance peripheral and any local RAM required.

摘要翻译： 本发明包括使用两个独立的完全自主的AHB总线的多事务高级高性能总线AHB系统，每个AHB总线具有其自己的总线仲裁系统，其具有解码以允许在两个AHB总线上的同时活动。 两条巴士与AHB至HTB总线桥分开并与其同步。 第一个总线，内存总线AHB包含CPU和DMA作为总线主机，外部存储器控制器和内部存储器作为从站。 第二个总线，数据传输总线HTB，包含高性能外设和任何需要的本地RAM。

公开(公告)号：US06760802B2

公开(公告)日：2004-07-06

申请号：US09932379

申请日：2001-08-17

申请人： Steven R. Jahnke ,  Hiromichi Hamakawa

发明人： Steven R. Jahnke ,  Hiromichi Hamakawa

IPC分类号： G06F1314

CPC分类号： G06F13/24 ,  G06F13/3625 ,  G06F13/4031

摘要： The time-out counter of this invention provides a capability in a bus bridge for a first bus master to generate a time-out interrupt on reads from a second bus device if it is not given control of the second bus within a certain time period when the time of arbitration on the second bus is excessive. The time-out counter is programmable up to 16-bits and allowing the software selection of the time-out length. This time-out feature is useful if the manner of arbitration used would otherwise allow the second bus master to have absolute control of the first bus. Address and data FIFO buffers are used for writes to a second bus device.

摘要翻译： 本发明的超时计数器提供总线桥接器中的能力，用于第一总线主机在第二总线设备读取时产生超时中断，如果在一定时间段内没有给予第二总线控制， 第二班车仲裁时间过长。 超时计数器可编程高达16位，允许软件选择超时长度。 如果所使用的仲裁的方式否则允许第二总线主机对第一总线进行绝对控制，则该超时功能是有用的。 地址和数据FIFO缓冲区用于写入第二总线设备。

公开(公告)号：US06859852B2

公开(公告)日：2005-02-22

申请号：US09932718

申请日：2001-08-17

申请人： Steven R. Jahnke ,  Hiromichi Hamakawa

发明人： Steven R. Jahnke ,  Hiromichi Hamakawa

IPC分类号： G06F13/362 ,  G06F12/00 ,  G06F13/14 ,  G06F13/36 ,  G06F13/364 ,  G06F13/38 ,  G06F13/40

CPC分类号： G06F13/364 ,  G06F13/4031

摘要： The immediate grant bus arbiter of this invention is a part in the implementation of a multiple transaction bus system. A bus bridge provides a means to connect two separate busses together and secure data integrity. The bus bridge is defined with clear master-slave protocol. The bus bridge normally involves the use of two arbiters. The arbiter on the primary bus needs to operate differently from the arbiter on the secondary bus due to real system time constraints. This invention defines a bus arbiter that allows for a dominant bus master to receive an immediate grant of control on the bus. This immediate grant bus arbiter never relinquishes the bus if another lower priority master makes a bus request. This makes predictable real time data transfer possible.

摘要翻译： 本发明的直接授权总线仲裁器是实现多事务总线系统的一部分。 总线桥提供了将两个单独的总线连接在一起并确保数据完整性的手段。 总线桥被定义为清晰的主从协议。 公共汽车桥通常涉及使用两个仲裁者。 由于实际的系统时间限制，主总线上的仲裁器需要与辅助总线上的仲裁器的操作不同。 本发明定义了总线仲裁器，其允许主要总线主控器在总线上立即接收对控制的授权。 如果另一个较低优先级的主人作出总线请求，这个立即授权总线仲裁者决不放弃总线。 这使得可预测的实时数据传输成为可能。

公开(公告)号：US06742058B2

公开(公告)日：2004-05-25

申请号：US10259552

申请日：2002-09-27

申请人： Steven R. Jahnke ,  Hiromichi Hamakawa ,  Naoto Mabuchi

发明人： Steven R. Jahnke ,  Hiromichi Hamakawa ,  Naoto Mabuchi

IPC分类号： G06F1314

CPC分类号： G06F13/1684 ,  G06F13/1694

摘要： A configurable memory controller for an AMBA system is described. This configurable memory controller selects one of two possible modes of operation. The technique of configuring the memory controller provides fundamental memory control in the AMBA system while also allowing for a switching mechanism to select between the two modes, each of which entails its own set of special signal definitions. The configurable memory controller may be connected either on the AHB bus or directly connected to the ARM central processing unit core with a mechanism to switch between the two modes of operation.

摘要翻译： 描述了用于AMBA系统的可配置的存储器控​​制器。 该可配置的存储器控​​制器选择两种可能的操作模式之一。 配置存储器控制器的技术在AMBA系统中提供基础存储器控制，同时还允许切换机制在两种模式之间进行选择，每种模式都需要其自己的一组特殊信号定义。 可配置的存储器控​​制器可以在AHB总线上连接或者直接连接到ARM中央处理器核心，并具有在两种操作模式之间切换的机制。

公开(公告)号：US07508728B2

公开(公告)日：2009-03-24

申请号：US11512675

申请日：2006-08-30

申请人： Steve Richard Jahnke ,  Hiromichi Hamakawa

发明人： Steve Richard Jahnke ,  Hiromichi Hamakawa

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40622 ,  G11C2207/104

摘要： Methods and apparatus to provide refresh when an out of range address is received are disclosed. An example method of providing a refresh signal to a memory cell includes receiving a memory address on address lines ranging from a most significant bit address line to a least significant bit address line. A memory driver logic device is coupled to the memory cell. An out of range logic decoder is coupled to provide a fixed logic input to a first input of the memory driver logic device. Address logic is provided to cause the memory driver logic device to enable the memory cell if the memory address is a local out of range address.

摘要翻译： 公开了当接收到超范围地址时提供刷新的方法和装置。 向存储器单元提供刷新信号的示例性方法包括在从最高有效位地址线到最低有效位地址线的地址线上接收存储器地址。 存储器驱动器逻辑器件耦合到存储器单元。 超范围逻辑解码器被耦合以向存储器驱动器逻辑器件的第一输入提供固定逻辑输入。 如果存储器地址是本地超出范围的地址，则提供地址逻辑以使存储器驱动器逻辑器件启用存储器单元。

公开(公告)号：US20080056043A1

公开(公告)日：2008-03-06

申请号：US11512675

申请日：2006-08-30

申请人： Steve Richard Jahnke ,  Hiromichi Hamakawa

发明人： Steve Richard Jahnke ,  Hiromichi Hamakawa

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40622 ,  G11C2207/104

摘要： Methods and apparatus to provide refresh when an out of range address is received are disclosed. An example method of providing a refresh signal to a memory cell includes receiving a memory address on address lines ranging from a most significant bit address line to a least significant bit address line. A memory driver logic device is coupled to the memory cell. An out of range logic decoder is coupled to provide a fixed logic input to a first input of the memory driver logic device. Address logic is provided to cause the memory driver logic device to enable the memory cell if the memory address is a local out of range address.

摘要翻译： 公开了当接收到超范围地址时提供刷新的方法和装置。 向存储器单元提供刷新信号的示例性方法包括在从最高有效位地址线到最低有效位地址线的地址线上接收存储器地址。 存储器驱动器逻辑器件耦合到存储器单元。 超范围逻辑解码器被耦合以向存储器驱动器逻辑器件的第一输入提供固定逻辑输入。 如果存储器地址是本地超出范围的地址，则提供地址逻辑以使存储器驱动器逻辑器件启用存储器单元。

公开(公告)号：US07518941B2

公开(公告)日：2009-04-14

申请号：US11512676

申请日：2006-08-30

申请人： Steven Richard Jahnke ,  Hiromichi Hamakawa

发明人： Steven Richard Jahnke ,  Hiromichi Hamakawa

IPC分类号： G11C8/00

CPC分类号： G11C8/12 ,  G11C8/10 ,  G11C11/413

摘要： Methods and apparatus to provide refresh for local out of range read requests for a memory device are disclosed. An example method disclosed herein provides a read signal to a memory cell. An address is received on row address lines ranging from a most significant bit row address line to a least significant bit row address line. A fixed high logic input is coupled to a first input of a row driver logic device associated with a local out of range address. Logic is provided to send a read enable signal on a bit line coupled to an output of the row driver logic device coupled to the memory cell if the address is the local out of range address.

摘要翻译： 公开了为存储器件的局部超范围读取请求提供刷新的方法和装置。 这里公开的示例性方法向存储器单元提供读取信号。 在从最高有效位行地址线到最低有效位行地址线的行地址线上接收地址。 固定的高逻辑输入耦合到与本地超出范围地址相关联的行驱动器逻辑器件的第一输入。 如果地址是本地超出范围地址，则提供逻辑以在耦合到耦合到存储器单元的行驱动器逻辑器件的输出的位线上发送读使能信号。

公开(公告)号：US20080056054A1

公开(公告)日：2008-03-06

申请号：US11512676

申请日：2006-08-30

申请人： Steven Richard Jahnke ,  Hiromichi Hamakawa

发明人： Steven Richard Jahnke ,  Hiromichi Hamakawa

IPC分类号： G11C8/00

CPC分类号： G11C8/12 ,  G11C8/10 ,  G11C11/413

摘要： Methods and apparatus to provide refresh for local out of range read requests for a memory device are disclosed. An example method disclosed herein provides a read signal to a memory cell. An address is received on row address lines ranging from a most significant bit row address line to a least significant bit row address line. A fixed high logic input is coupled to a first input of a row driver logic device associated with a local out of range address. Logic is provided to send a read enable signal on a bit line coupled to an output of the row driver logic device coupled to the memory cell if the address is the local out of range address.

摘要翻译： 公开了为存储器件的局部超范围读取请求提供刷新的方法和装置。 这里公开的示例性方法向存储器单元提供读取信号。 在从最高有效位行地址线到最低有效位行地址线的行地址线上接收地址。 固定的高逻辑输入耦合到与本地超出范围地址相关联的行驱动器逻辑器件的第一输入。 如果地址是本地超出范围地址，则提供逻辑以在耦合到耦合到存储器单元的行驱动器逻辑器件的输出的位线上发送读使能信号。