A data communications subsystem (15) including a digital signal processor (DSP) (20) for performing bit insertion to preclude the inadvertent serial transmission of a protocol flag sequence is disclosed. A trigger sequence detection process (40) applies an infinite impulse response (IIR) filter to a current sequence of the input bitstream to generate a insertion bitstream that is bit sychronized with the the input bitstream. A bit insertion process (50) then inserts bits into the input bitstream at bit positions indicated by the insertion bitstream. The trigger sequence detection process (40) may be applied to subsequent sections of the input bitstream, as it is not dependent upon the results of the bit insertion process (50).