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公开(公告)号：US08683133B2
公开(公告)日：2014-03-25
申请号：US12356303
申请日：2009-01-20
CPC分类号： G06F12/0862 , G06F13/16 , G06F2212/1032 , Y02D10/13 , Y02D10/14
摘要： A real request from a CPU to the same memory bank as a prior prefetch request is transmitted to the per-memory bank logic along with a kill signal to terminate the prefetch request. This avoids waiting for a prefetch request to complete before sending the real request to the same memory bank. The kill signal gates off any acknowledgement of completion of the prefetch request. This invention reduces the latency for completion of a high priority real request when a low priority speculative request to a different address in the same memory bank has already been dispatched.
摘要翻译： 与先前的预取请求相关联的来自CPU到同一存储体的实际请求将与杀死信号一起发送到每存储器存储体逻辑以终止预取请求。 这避免了在将实际请求发送到同一个存储体之前等待预取请求完成。 杀死信号禁止任何完成预取请求的确认。 当对同一存储体中的不同地址的低优先级推测请求已经被分派时，本发明减少了完成高优先级实际请求的等待时间。
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公开(公告)号：US20090249105A1
公开(公告)日：2009-10-01
申请号：US12356274
申请日：2009-01-20
CPC分类号： G06F12/0862 , G06F13/16 , G06F2212/1032 , Y02D10/13 , Y02D10/14
摘要： This invention manages power down and wakeup of shared memories in a multiprocessor system. A register for each shared memory has bits corresponding to each master. When a master wants to power down a memory, it sets its corresponding bit in the register. A hardware power down controller for the memory bank powers the memory bank if any processor signals powering the memory bank. The hardware power down controller for the memory bank powers down the memory bank only if all processor signal powering down the memory bank. waits for all masters to set their corresponding bits in the register before initiating power down of the memories. Software running on any processor has a view of the shared memory independent of the other processors and no inter-processor communication is needed.
摘要翻译： 本发明管理多处理器系统中的共享存储器的掉电和唤醒。 每个共享存储器的寄存器具有与每个主器件相对应的位。 当主机要关闭存储器时，它将其相应的位置于寄存器中。 如果任何处理器信号为存储体供电，则存储器组件的硬件掉电控制器为存储体供电。 存储器的硬件掉电控制器只有在所有处理器信号使存储器电源断电的情况下才能关闭存储器。 在启动存储器掉电之前，等待所有主机在寄存器中设置相应的位。 在任何处理器上运行的软件具有独立于其他处理器的共享存储器的视图，并且不需要处理器间通信。
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3.发明申请Upgrade of Low Priority Prefetch Requests to High Priority Real Requests in Shared Memory Controller 有权将低优先级预取请求升级到共享内存控制器中的高优先级实时请求公开(公告)号：US20090248992A1
公开(公告)日：2009-10-01
申请号：US12356308
申请日：2009-01-20
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F13/16 , G06F2212/1032 , Y02D10/13 , Y02D10/14
摘要： A prefetch controller implements an upgrade when a real read access request hits the same memory bank and memory address as a previous prefetch request. In response per-memory bank logic promotes the priority of the prefetch request to that of a read request. If the prefetch request is still waiting to win arbitration, this upgrade in priority increases the likelihood of gaining access generally reducing the latency. If the prefetch request had already gained access through arbitration, the upgrade has no effect. This thus generally reduces the latency in completion of a high priority real request when a low priority speculative prefetch was made to the same address.
摘要翻译： 当实际读取访问请求与先前的预取请求相同时，预取控制器实现升级。 响应每存储器存储器逻辑将预取请求的优先级提升为读取请求的优先级。 如果预取请求仍在等待赢得仲裁，则此优先级升级增加了获取访问的可能性通常会降低延迟。 如果预取请求已经通过仲裁获得访问权限，则升级不起作用。 因此，当对相同地址进行低优先级推测预取时，这通常降低了完成高优先级实际请求时的等待时间。
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公开(公告)号：US07576758B2
公开(公告)日：2009-08-18
申请号：US11370533
申请日：2006-03-08
IPC分类号： G09G5/00
CPC分类号： G06T3/606
摘要： Rotation in the storage domain is a one-one function with the domain equal to the range. This permits an image to be rotated in place. Each image size implies at least one garland of closed chains of tiles. Each image includes a spanning set of these garlands. Rotation in place moves each pixel to the next location on its garland. On completion of a garland by return to the initial tile, tiles on the next garland are moved. Image rotation is complete after all the garlands have been traversed. This invention first linearized the two-dimensional tiles sliding into groups of super-pixels at contiguous locations above the image buffer. The tiles are rotated in place. The shuffled tiles are delinearized into rectangular blocks and then re-pitched if needed.
摘要翻译： 存储域中的旋转是一个单一函数，其域等于该范围。 这允许图像旋转到位。 每个图像大小意味着至少一个封闭的瓦片链的花环。 每个图像包括这些花环的跨越。 旋转到位将每个像素移动到其花环上的下一个位置。 通过返回初始瓷砖完成花环，下一个花环上的瓷砖被移动。 所有花环遍历后，图像旋转完成。 本发明首先将二维瓦片线性化成在图像缓冲器上方的连续位置滑动成超像素组。 瓦片旋转到位。 洗牌砖被划分成矩形块，然后如果需要重新调整。
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5.发明授权Direct memory access channel controller with quick channels, event queue and active channel memory protection 有权直接内存访问通道控制器，具有快速通道，事件队列和主动通道内存保护公开(公告)号：US07546391B2
公开(公告)日：2009-06-09
申请号：US11383045
申请日：2006-05-12
IPC分类号： G06F13/28 , G06F13/36 , G06F15/167 , G06F12/00
CPC分类号： G06F13/28
摘要： A data transfer control apparatus includes a channel controller and a transfer controller. The channel controller receives, prioritizes and queues event signals and predetermined memory writes which trigger data transfer requests controlling the transfer controller. The event queue stores event numbers mapped to parameter memory locations storing data transfer parameters. The mapping table and the parameter memory are writeable via a memory mapped write operation. Memory protection registers store data indicative of permitted data accesses to the memory map.
摘要翻译： 数据传送控制装置包括通道控制器和传送控制器。 通道控制器接收，优先排序和排队触发控制传输控制器的数据传输请求的事件信号和预定的存储器写入。 事件队列存储映射到存储数据传输参数的参数存储单元的事件号。 映射表和参数存储器可通过存储器映射写操作进行写入。 存储器保护寄存器存储表示允许的数据访问存储器映射的数据。
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公开(公告)号：US06574724B1
公开(公告)日：2003-06-03
申请号：US09702474
申请日：2000-10-31
IPC分类号： G06F1200
CPC分类号： G06F9/3828 , G06F9/30181 , G06F9/3555
摘要： A data processing system having a central processing (CPU) unit and a method of operation is provided. The CPU has an instruction set architecture that is optimized for intensive numeric algorithm processing. The CPU has dual load/store units connected to dual memory target ports of a memory controller. The CPU can execute two aligned data transfers each having a length of one byte, two bytes, four bytes, or eight bytes in parallel by executing two load/store instructions. The CPU can also execute a single non-aligned data transfer having a length of four bytes or eight bytes by executing a non-aligned load/store instruction that utilizes both memory target ports. A data transfer address for each load/store instruction is formed by fetching the instruction, decoding the instruction to determine instruction type, transfer data size, and scaling selection, selectively scaling an offset provided by the instruction and combining the selectively scaled offset with a base address value. The resultant address is then provided to the memory system to initiate a data transfer.
摘要翻译： 提供具有中央处理（CPU）单元和操作方法的数据处理系统。 CPU具有针对密集数值算法处理进行了优化的指令集体系结构。 CPU具有连接到存储器控制器的双存储器目标端口的双重加载/存储单元。 CPU可以通过执行两个加载/存储指令来并行执行两个对齐的数据传输，每个数据传输具有一个字节，两个字节，四个字节或八个字节的长度。 CPU还可以通过执行利用两个存储器目标端口的不对齐的加载/存储指令来执行长度为四字节或八字节的单个非对齐数据传输。 每个加载/存储指令的数据传输地址通过取指令，解码指令来确定指令类型，传输数据大小和缩放选择来形成，选择性地缩放由指令提供的偏移量，并将选择性缩放的偏移量与基数 地址值。 然后将结果地址提供给存储器系统以发起数据传送。
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公开(公告)号：US08301928B2
公开(公告)日：2012-10-30
申请号：US12356294
申请日：2009-01-20
申请人： Sajish Sajayan , Alok Anand , Joseph R. Zbiciak
发明人： Sajish Sajayan , Alok Anand , Joseph R. Zbiciak
IPC分类号： G06F1/00
CPC分类号： G06F12/0862 , G06F13/16 , G06F2212/1032 , Y02D10/13 , Y02D10/14
摘要： A hardware based wake-up scheme initiates memory power-up upon a normal access to a powered down memory. The access that triggered the power-up is buffered. Further accesses are stalled until the memory is completely powered up. The buffered access then proceeds to the memory and the processor is brought out of stall. In cases where the software does not directly control access to the memory, such as on a cache miss, this scheme avoids undesirable conditions due to access to powered down memories.
摘要翻译： 基于硬件的唤醒方案在正常访问掉电存储器时启动内存上电。 触发上电的访问被缓冲。 进一步的访问停止，直到内存完全通电。 然后，缓冲的访问进行到存储器，并且处理器被摆脱失速。 在软件不直接控制访问存储器（例如高速缓存未命中）的情况下，该方案避免了由于访问掉电存储器而导致的不期望的状况。
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公开(公告)号：US20120272027A1
公开(公告)日：2012-10-25
申请号：US13204002
申请日：2011-08-05
申请人： Joseph R. Zbiciak
发明人： Joseph R. Zbiciak
IPC分类号： G06F12/14
CPC分类号： G06F12/1483 , G06F12/14 , G06F12/1425 , G06F12/1433 , G06F12/1441 , G06F12/1458 , G06F12/1491 , G06F13/366 , G06F21/78 , G06F21/79 , G06F2212/1052 , Y02D10/14
摘要： A memory management and protection system that manages memory access requests from a number of requestors. Memory accesses are allowed or disallowed based on the permissions assigned to the request based on the memory segment being accessed. The decision to allow or disallow access is made by the extended memory controller by merging the permissions assigned to the memory segment being accessed, and the permissions assigned to the access request by the originating memory controller or other endpoint.
摘要翻译： 一种管理来自多个请求者的存储器访问请求的存储器管理和保护系统。 基于正在访问的存储器段，基于分配给请求的许可，允许或不允许存储器访问。 扩展内存控制器通过合并分配给正在访问的内存段的权限以及由始发内存控制器或其他端点分配给访问请求的权限，来决定是否允许访问。
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公开(公告)号：US07890566B1
公开(公告)日：2011-02-15
申请号：US09703034
申请日：2000-10-31
申请人： Joseph R. Zbiciak
发明人： Joseph R. Zbiciak
IPC分类号： G06F7/38
CPC分类号： G06F9/30014 , G06F7/49963 , G06F7/5443
摘要： A functional unit in a digital system is provided with a rounding DOT product instruction, wherein a product of first pair of elements is combined with a product of second pair of elements, the combined product is rounded, and the final result is stored in a destination. Rounding is performed by adding a rounding value to form an intermediate result, and then shifting the intermediate result right. A combined result is rounded to a fixed length shorter than the combined product. The products are combined by either addition or subtraction. An overflow resulting from the combination or from rounding is not reported.
摘要翻译： 数字系统中的功能单元具有舍入DOT产品指令，其中第一对元件的乘积与第二对元件的乘积组合，组合产品被舍入，最终结果存储在目的地 。 通过添加舍入值以形成中间结果来执行舍入，然后将中间结果右移。 组合的结果被舍入到比组合产品短的固定长度。 产品通过加法或减法组合。 没有报告由组合或四舍五入引起的溢出。
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10.发明授权Microprocessor with instructions for shifting data responsive to a signed count value 有权微处理器，具有响应于带符号计数值移位数据的指令公开(公告)号：US06757819B1
公开(公告)日：2004-06-29
申请号：US09703141
申请日：2000-10-31
申请人： David Hoyle , Richard H. Scales , Min Wang , Joseph R. Zbiciak
发明人： David Hoyle , Richard H. Scales , Min Wang , Joseph R. Zbiciak
IPC分类号： G06F1582
CPC分类号： G06F9/30032 , G06F9/30072
摘要： A data processing system is provided with a digital signal processor which has an instruction for shifting a source operand in response to a signed shift count value and storing the shifted result in a selected destination register. A first 32-bit operand (600) is treated as a signed shift value that has a sign and a shift count value. A second operand (602) is shifted by an amount according to the shift count value and in a direction according to the sign of the shift count. One instruction is provided that performs a right shift for a positive shift count and a left shift for a negative shift count, and another instruction is provided performs a left shift for a positive shift count and a right shift for a negative shift count. If the shift count value is greater than 31, then the shift is limited to 31.
摘要翻译： 数据处理系统具有数字信号处理器，该数字信号处理器具有响应于有符号移位计数值移位源操作数并将移位结果存储在所选择的目标寄存器中的指令。 第一个32位操作数（600）被视为具有符号和移位计数值的有符号位移值。 第二操作数（602）根据移位计数值和根据移位计数的符号的方向移位量。 提供一个指令，其执行用于正移位计数的右移位和用于负移位计数的左移位，并且提供另一指令来执行用于正移位计数的左移位和负移位计数的右移位。 如果移位计数值大于31，则移位限制为31。
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