A memory control device for arbitrating memory access contention among bus masters while ensuring, regarding each bus master, the required transfer rate within the required time margin. A device external to LSI 100 writes into the transfer rate information storage unit 111 the transfer rate information indicating the transfer rate and the time period within which the transfer rate is to be ensured. In response, the timing information generator unit 112 determines the shortest time period as a cycle, and also determines, regarding each bus master, time taken to ensure the required transfer rate based on the memory bus bandwidth as a bus use permission time period. The arbiter unit 114 grants the bus use right sequentially with the passage of time to each bus master issuing a bus request for the corresponding bus use permission time period.