A continuous-time baseline restoration (BLR) circuit providing built-in pulse tail-cancellation, or BLR tail-cancel circuit, in constant fraction discriminator (CFD) arming and timing circuits. The BLR tail cancel circuit is applied at the output of constant fraction timing shaping filters and arming circuits to permit monolithic integrated circuit implementation of CFD circuits operating at high input signal count rates. The BLR tail-cancel circuit provides correction of dc offset and count-rate dependent baseline errors along with simultaneous tail-cancellation. Correction of dc offsets due to electronic device mismatches and count-rate dependent baseline errors is required for accurate time pickoff from the input signals. The reduction of pulse width, or pulse tail-cancellation is required to shorten the duration of high count rate signals to prevent the severe distortion caused by the occurrence a new signal superimposed on the tails of previous signals, a condition known as pulse pileup. Without pulse tail-cancellation, there are substantial errors in time pickoff due to the pulse pileup.