发明授权
- 专利标题： On chip resistor calibration structure and method
- 专利标题（中）： 片上电阻校准结构及方法
-
申请号： US10605567申请日： 2003-10-09
-
公开(公告)号： US06825490B1公开(公告)日： 2004-11-30
- 发明人: Terence B. Hook , Raminderpal Singh , Stephen D. Wyatt
- 申请人： Terence B. Hook , Raminderpal Singh , Stephen D. Wyatt
- 主分类号： H01L2358
- IPC分类号： H01L2358
摘要：
A structure and associated method to determine an actual resistance value of a calibration resistor within a semiconductor device. The semiconductor device comprises a capacitor, a calibration resistor, and a calibration circuit. A voltage applied to the calibration resistor produces a current flow through the calibration resistor to charge the capacitor. The calibration circuit is adapted to measure an actual time required to charge the capacitor. The calibration circuit is further adapted calculate an actual resistance value of the calibration resistor based on the actual time required to charge the capacitor and a capacitance value of the capacitor.
信息查询
