发明授权
US06828644B2 Semiconductor device with reduced parasitic capacitance between impurity diffusion regions
有权
具有降低杂质扩散区域之间的寄生电容的半导体器件
- 专利标题： Semiconductor device with reduced parasitic capacitance between impurity diffusion regions
- 专利标题（中）： 具有降低杂质扩散区域之间的寄生电容的半导体器件
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申请号： US10393389申请日： 2003-03-21
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公开(公告)号： US06828644B2公开(公告)日： 2004-12-07
- 发明人: Yuji Asano , Morio Katou , Takao Setoyama , Toshihiko Fukushima , Kazuhiro Natsuaki
- 申请人： Yuji Asano , Morio Katou , Takao Setoyama , Toshihiko Fukushima , Kazuhiro Natsuaki
- 优先权： JP2002-081041 20020322
- 主分类号： H01L3106
- IPC分类号： H01L3106
摘要：
A first layer is formed on an underlying substrate having a surface layer made of semiconductor of a first conductivity type. The first layer is made of semiconductor having a resistance higher than that of the surface layer. A first impurity diffusion region of a second conductivity type is formed in a partial surface region of the first layer. The first impurity diffusion region does not reach the surface of the underlying substrate. A second impurity diffusion region of the first conductivity type is disposed in the first layer and spaced apart from the first impurity diffusion region. The second impurity diffusion region reaches the surface of the underlying substrate. A separation region is disposed between the first and second impurity diffusion regions. The separation region comprises a trench formed in the first layer and dielectric material disposed at least in a partial internal region of the trench.
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