Invention Grant
- Patent Title: Power MOS transistor for absorbing surge current
- Patent Title (中): 功率MOS晶体管,用于吸收浪涌电流
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Application No.: US09945621Application Date: 2001-09-05
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Publication No.: US06831331B2Publication Date: 2004-12-14
- Inventor: Yasuhiro Kitamura , Toshio Sakakibara , Kenji Kohno , Shoji Mizuno , Yoshiaki Nakayama , Hiroshi Maeda , Makio Iida , Hiroshi Fujimoto , Mitsuhiro Saitou , Hiroshi Imai , Hiroyuki Ban
- Applicant: Yasuhiro Kitamura , Toshio Sakakibara , Kenji Kohno , Shoji Mizuno , Yoshiaki Nakayama , Hiroshi Maeda , Makio Iida , Hiroshi Fujimoto , Mitsuhiro Saitou , Hiroshi Imai , Hiroyuki Ban
- Priority: JP7-297148 19951115; JP8-8699 19960122; JP8-211675 19960809; JP8-250299 19960920
- Main IPC: H01L2976
- IPC: H01L2976

Abstract:
A semiconductor device is provided having a power transistor structure. The power transistor structure includes a plurality of first wells disposed independently at a surface portion of a semiconductor layer; a deep region having a portion disposed in the semiconductor layer between the first wells; a drain electrode connected to respective drain regions in the first wells; a source electrode connected to respective source regions and channel well regions in the first wells, such that either the drain electrode or the source electrode is connected to an inductive load; and a connecting member for supplying the deep region with a source potential, where the connecting member is configurable to connect to the drain electrode when the drain electrode is connected to the inductive load and to connect to the source electrode when the source electrode is connected to said inductive load.
Public/Granted literature
- US20020017697A1 Semiconductor device and manufacturing method thereof Public/Granted day:2002-02-14
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