公开(公告)号：US08815701B2

公开(公告)日：2014-08-26

申请号：US13546040

申请日：2012-07-11

Applicant: Masakiyo Sumitomo ,  Makoto Asai ,  Nozomu Akagi ,  Yasuhiro Kitamura ,  Hiroki Nakamura ,  Tetsuo Fujii

Inventor： Masakiyo Sumitomo ,  Makoto Asai ,  Nozomu Akagi ,  Yasuhiro Kitamura ,  Hiroki Nakamura ,  Tetsuo Fujii

IPC: H01L21/762 ,  H01L27/12 ,  H01L27/06 ,  H01L21/8234 ,  H01L27/02 ,  H01L21/84 ,  H01L29/06 ,  H01L29/78 ,  H01L21/265

CPC classification number: H01L21/823481 ,  H01L21/26533 ,  H01L21/76243 ,  H01L21/76264 ,  H01L21/823487 ,  H01L21/84 ,  H01L27/0251 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes: a SOI substrate including a support layer, a first insulation film and a SOI layer; a first circuit; a second circuit; and a trench separation element. The SOI substrate further includes a first region and a second region. The first region has the support layer, the first insulation film and the SOI layer, which are stacked in this order, and the second region has only the support layer. The trench separation element penetrates the support layer, the first insulation film and the SOI layer. The trench separation element separates the first region and the second region. The first circuit is disposed in the SOI layer of the first region. The second circuit is disposed in the support layer of the second region.

Abstract translation: 半导体器件包括：SOI衬底，包括支撑层，第一绝缘膜和SOI层; 第一个电路; 第二电路; 和沟槽分离元件。 SOI衬底还包括第一区域和第二区域。 第一区域具有依次层叠的支撑层，第一绝缘膜和SOI层，第二区域仅具有支撑层。 沟槽分离元件穿透支撑层，第一绝缘膜和SOI层。 沟槽分离元件分离第一区域和第二区域。 第一电路设置在第一区域的SOI层中。 第二电路设置在第二区域的支撑层中。

公开(公告)号：US20120302036A1

公开(公告)日：2012-11-29

申请号：US13546040

申请日：2012-07-11

Applicant: Masakiyo Sumitomo ,  Makoto Asai ,  Nozomu Akagi ,  Yasuhiro Kitamura ,  Hiroki Nakamura ,  Tetsuo Fujii

Inventor： Masakiyo Sumitomo ,  Makoto Asai ,  Nozomu Akagi ,  Yasuhiro Kitamura ,  Hiroki Nakamura ,  Tetsuo Fujii

IPC: H01L21/762

CPC classification number: H01L21/823481 ,  H01L21/26533 ,  H01L21/76243 ,  H01L21/76264 ,  H01L21/823487 ,  H01L21/84 ,  H01L27/0251 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes: a SOI substrate including a support layer, a first insulation film and a SOI layer; a first circuit; a second circuit; and a trench separation element. The SOI substrate further includes a first region and a second region. The first region has the support layer, the first insulation film and the SOI layer, which are stacked in this order, and the second region has only the support layer. The trench separation element penetrates the support layer, the first insulation film and the SOI layer. The trench separation element separates the first region and the second region. The first circuit is disposed in the SOI layer of the first region. The second circuit is disposed in the support layer of the second region.

Abstract translation: 半导体器件包括：SOI衬底，包括支撑层，第一绝缘膜和SOI层; 第一个电路; 第二电路; 和沟槽分离元件。 SOI衬底还包括第一区域和第二区域。 第一区域具有依次层叠的支撑层，第一绝缘膜和SOI层，第二区域仅具有支撑层。 沟槽分离元件穿透支撑层，第一绝缘膜和SOI层。 沟槽分离元件分离第一区域和第二区域。 第一电路设置在第一区域的SOI层中。 第二电路设置在第二区域的支撑层中。

公开(公告)号：US08314459B2

公开(公告)日：2012-11-20

申请号：US12805420

申请日：2010-07-30

Applicant: Yasuhiro Kitamura

Inventor： Yasuhiro Kitamura

IPC: H01L29/66

CPC classification number: H01L21/823487 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L27/088 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/48463 ,  H01L2224/49111 ,  H01L2224/494 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/12036 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device includes a semiconductor substrate, a vertical transistor, a horizontal transistor, a lead, wire-bonding pads, and penetrating electrodes. The semiconductor substrate has first and second surfaces and includes a first surface portion adjacent to the first surface. The vertical transistor includes first and second electrodes on the first surface and a third electrode on the second surface. The horizontal transistor includes first, second, and third electrodes on the first surface. The vertical transistor and the horizontal transistor further include PN junction parts in the first surface portion. The lead is disposed to the first surface and is electrically coupled with the first electrode of the vertical transistor. The wire-bonding pads are disposed on the second surface. The second electrode of the vertical transistor and the first to third electrodes of the horizontal transistor are electrically coupled with the wire-boding pads through the penetrating electrodes.

Abstract translation: 半导体器件包括半导体衬底，垂直晶体管，水平晶体管，引线，引线接合焊盘和穿透电极。 半导体衬底具有第一表面和第二表面，并且包括与第一表面相邻的第一表面部分。 垂直晶体管包括第一表面上的第一和第二电极以及第二表面上的第三电极。 水平晶体管包括第一表面上的第一，第二和第三电极。 垂直晶体管和水平晶体管还包括第一表面部分中的PN结部分。 引线设置在第一表面上并与垂直晶体管的第一电极电耦合。 引线接合焊盘设置在第二表面上。 垂直晶体管的第二电极和水平晶体管的第一至第三电极通过穿透电极与引线焊盘电耦合。

公开(公告)号：US08610246B2

公开(公告)日：2013-12-17

申请号：US13084074

申请日：2011-04-11

Applicant: Shinji Yoshihara ,  Kazushi Asami ,  Yasuhiro Kitamura ,  Junji Oohara

Inventor： Shinji Yoshihara ,  Kazushi Asami ,  Yasuhiro Kitamura ,  Junji Oohara

IPC: H01L29/00

CPC classification number: H01L21/6835 ,  H01F5/003 ,  H01F41/041 ,  H01F41/046 ,  H01L2924/0002 ,  H05K1/165 ,  H05K2201/09672 ,  H01L2924/00

Abstract: In a manufacturing method for a semiconductor device having a coil layer part on a substrate, two support substrates each having a flat surface are prepared, and a component member is formed on the flat surface of each of the support substrates. The component member includes a wiring portion having a predetermined pattern and an insulation film surrounding the wiring portion. The wiring portion is provided with a connecting portion exposing from the insulation film. A coil layer part is formed by opposing and bonding the component members formed on the support substrates to each other while applying pressure in a condition where the flat surfaces of the support substrates are parallel to each other. A coil is formed in the coil layer part by connecting the wiring portions through the connecting portions.

Abstract translation: 在具有在基板上具有线圈层部分的半导体器件的制造方法中，准备了具有平坦表面的两个支撑基板，并且在每个支撑基板的平坦表面上形成有部件。 该部件包括具有预定图案的布线部分和围绕布线部分的绝缘膜。 布线部分设置有从绝缘膜露出的连接部分。 线圈层部分通过在支撑基板的平坦表面彼此平行的状态下相对地并且将形成在支撑基板上的部件彼此相对并粘合而形成，同时施加压力。 通过连接部分连接布线部分，在线圈层部分中形成线圈。

公开(公告)号：US20120080772A1

公开(公告)日：2012-04-05

申请号：US13246065

申请日：2011-09-27

Applicant: Kazushi Asami ,  Yasuhiro Kitamura

Inventor： Kazushi Asami ,  Yasuhiro Kitamura

IPC: H01L29/92 ,  H01L21/02

CPC classification number: H01L28/91 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/642 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate, a first single conductor, a single insulator, and a second single conductor. The substrate includes first and second regions located adjacent to each other. The first region has blind holes, each of which has an opening on a front surface of the substrate. The second region has a through hole penetrating the substrate. A width of each blind hole is less than a width of the through hole. The first single conductor is formed on the front surface of the substrate in such a manner that an inner surface of each blind hole and an inner surface of the through hole are covered with the first single conductor. The single insulator is formed on the first single conductor. The second single conductor is formed on the single insulator and electrically insulated form the first single conductor.

Abstract translation: 半导体器件包括衬底，第一单导体，单绝缘体和第二单导体。 衬底包括彼此相邻定位的第一和第二区域。 第一区域具有盲孔，每个盲孔在基板的前表面上具有开口。 第二区域具有穿透基板的通孔。 每个盲孔的宽度小于通孔的宽度。 第一单导体形成在基板的前表面上，使得每个盲孔的内表面和通孔的内表面被第一单导体覆盖。 单个绝缘体形成在第一单个导体上。 第二单导体形成在单个绝缘体上并且电绝缘形成第一单导体。

公开(公告)号：US20120062859A1

公开(公告)日：2012-03-15

申请号：US13225061

申请日：2011-09-02

Applicant: YASUHIRO KITAMURA

Inventor： YASUHIRO KITAMURA

IPC: G03B27/52

CPC classification number: G03F7/70341

Abstract: An exposure apparatus includes a projection optical system and a liquid supply device. The projection optical system includes an image plane side optical member, which is arranged in an optical path of exposure light, and a lens barrel, which supports the image plane side optical member. The liquid supply device polishes the image plane side optical member in a state supported by the lens barrel to change the shape of the image plane side optical member.

Abstract translation: 曝光装置包括投影光学系统和液体供应装置。 投影光学系统包括布置在曝光光的光路中的像平面侧光学构件和支撑像面侧光学构件的透镜镜筒。 液体供应装置以由镜筒支撑的状态抛光图像平面侧光学构件，以改变像面侧光学构件的形状。

公开(公告)号：US20100295170A1

公开(公告)日：2010-11-25

申请号：US12785764

申请日：2010-05-24

Applicant: Atsushi KOMURA ,  Yasuhiro Kitamura ,  Nozomu Akagi ,  Yasutomi Asai

Inventor： Atsushi KOMURA ,  Yasuhiro Kitamura ,  Nozomu Akagi ,  Yasutomi Asai

IPC: H01L23/485 ,  H01L23/367

CPC classification number: H01L24/05 ,  H01L23/3677 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/06181 ,  H01L2224/13083 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24226 ,  H01L2224/25171 ,  H01L2224/25174 ,  H01L2224/2518 ,  H01L2224/80855 ,  H01L2224/81203 ,  H01L2224/8184 ,  H01L2224/82 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19043 ,  H05K1/0204 ,  H05K1/186 ,  H05K3/4617 ,  H05K3/4644 ,  H05K2201/10416 ,  H05K2203/063 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device includes a multilayer wiring substrate and a double-sided multi-electrode chip. The double-sided multi-electrode chip includes a semiconductor chip and has multiple electrodes on both sides of the semiconductor chip. The double-sided multi-electrode chip is embedded in the multilayer wiring substrate in such a manner that the double-sided multi-electrode chip is not exposed outside the multilayer wiring substrate. The electrodes of the double-sided multi-electrode chip are connected to wiring layers of the multilayer wiring substrate.

Abstract translation: 半导体器件包括多层布线基板和双面多电极芯片。 双面多电极芯片包括半导体芯片，并且在半导体芯片的两侧具有多个电极。 双面多电极芯片以这样的方式嵌入多层布线基板中，使得双面多电极芯片不暴露在多层布线基板的外部。 双面多电极芯片的电极连接到多层布线基板的布线层。

公开(公告)号：US20090057812A1

公开(公告)日：2009-03-05

申请号：US12230209

申请日：2008-08-26

Applicant: Nozomu Akagi ,  Yasuhiro Kitamura ,  Tetsuo Fujii

Inventor： Nozomu Akagi ,  Yasuhiro Kitamura ,  Tetsuo Fujii

IPC: H01L29/06 ,  H01L21/76

CPC classification number: H01L21/76264 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: In a manufacturing of a semiconductor device, at least one of elements is formed in each of element formation regions of a substrate having a main side and a rear side, and the substrate is thinned by polished from a rear side of the substrate, and then, multiple trenches are formed on the rear side of the substrate, so that each trench reaches the main side of the substrate. After that, an insulating material is deposited over an inner surface of each trench to form an insulating layer in the trench, so that the element formation regions are isolated. Thereby, generation of cracks and structural steps in the substrate and separation of element formation regions from the substrate can be suppressed.

Abstract translation: 在半导体器件的制造中，在具有主侧和后侧的基板的元件形成区域中的至少一个元件形成区域中形成至少一个元件，并且通过从基板的后侧抛光基板而使基板变薄 在衬底的后侧形成多个沟槽，使得每个沟槽到达衬底的主侧。 之后，绝缘材料沉积在每个沟槽的内表面上，以在沟槽中形成绝缘层，使得元件形成区域被隔离。 由此，可以抑制基板的裂纹和结构的产生，并且能够抑制元件形成区域与基板的分离。

公开(公告)号：US06831331B2

公开(公告)日：2004-12-14

申请号：US09945621

申请日：2001-09-05

Applicant: Yasuhiro Kitamura ,  Toshio Sakakibara ,  Kenji Kohno ,  Shoji Mizuno ,  Yoshiaki Nakayama ,  Hiroshi Maeda ,  Makio Iida ,  Hiroshi Fujimoto ,  Mitsuhiro Saitou ,  Hiroshi Imai ,  Hiroyuki Ban

Inventor： Yasuhiro Kitamura ,  Toshio Sakakibara ,  Kenji Kohno ,  Shoji Mizuno ,  Yoshiaki Nakayama ,  Hiroshi Maeda ,  Makio Iida ,  Hiroshi Fujimoto ,  Mitsuhiro Saitou ,  Hiroshi Imai ,  Hiroyuki Ban

IPC: H01L2976

CPC classification number: H01L29/7816 ,  H01L21/8249 ,  H01L27/0251 ,  H01L27/0623 ,  H01L27/085 ,  H01L29/1087 ,  H01L29/66674 ,  H01L29/7395 ,  H01L29/7801 ,  H01L29/7824 ,  H01L29/7835

Abstract: A semiconductor device is provided having a power transistor structure. The power transistor structure includes a plurality of first wells disposed independently at a surface portion of a semiconductor layer; a deep region having a portion disposed in the semiconductor layer between the first wells; a drain electrode connected to respective drain regions in the first wells; a source electrode connected to respective source regions and channel well regions in the first wells, such that either the drain electrode or the source electrode is connected to an inductive load; and a connecting member for supplying the deep region with a source potential, where the connecting member is configurable to connect to the drain electrode when the drain electrode is connected to the inductive load and to connect to the source electrode when the source electrode is connected to said inductive load.

Abstract translation: 提供具有功率晶体管结构的半导体器件。 功率晶体管结构包括独立地设置在半导体层的表面部分处的多个第一阱; 深部区域，其具有设置在所述第一阱之间的所述半导体层中的部分; 漏电极，连接到所述第一阱中的相应的漏极区; 源电极，其连接到第一阱中的各个源极区域和沟道阱区域，使得漏极电极或源极电极连接到感性负载; 以及连接构件，用于向深区域提供源极电位，其中当漏电极连接到感性负载时，连接构件可配置为连接到漏电极，并且当源电极连接到源电极时连接到源电极 表示感性负载。

公开(公告)号：US4840630A

公开(公告)日：1989-06-20

申请号：US154504

申请日：1988-02-04

Applicant: Yasuhiro Kitamura

Inventor： Yasuhiro Kitamura

IPC: A61F2/00 ,  A61F2/32 ,  A61F2/34 ,  A61F2/36

CPC classification number: A61F2/32 ,  A61F2/3662 ,  A61F2002/30084 ,  A61F2002/3085 ,  A61F2002/3611 ,  A61F2310/00179 ,  A61F2310/00203

Abstract: An artificial hip joint for connecting a hipbone with a thighbone is disclosed. Its external frame member to be secured in the hipbone, at least the section directly contacting the hipbone, is made of ceramic material, and a socket plug for rotatably supporting the condyle of a stem member is made of plastic material.

Abstract translation: 公开了一种用于连接髋骨与大腿骨的人造髋关节。 其外框架构件被固定在髋骨中，至少直接接触髋骨的部分由陶瓷材料制成，并且用于可旋转地支撑杆构件的髁的插座用塑料制成。