Invention Grant
- Patent Title: I/O cell and ESD protection circuit
- Patent Title (中): I / O单元和ESD保护电路
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Application No.: US10454710Application Date: 2003-06-04
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Publication No.: US06838708B2Publication Date: 2005-01-04
- Inventor: Shi-Tron Lin , Wei-Fan Chen
- Applicant: Shi-Tron Lin , Wei-Fan Chen
- Applicant Address: TW
- Assignee: Winbond Electronics Corp.
- Current Assignee: Winbond Electronics Corp.
- Current Assignee Address: TW
- Agent Raymond Sun
- Main IPC: H01L27/02
- IPC: H01L27/02 ; H01L29/74 ; H01L31/111
Abstract:
An ESD protection circuit has a VDD bus, a VSS bus, an IC pad, a PMOS transistor coupled to the IC pad and the VDD bus, and an NMOS transistor coupled to the IC pad and the VSS bus. The pitch of the PMOS can smaller than the pitch of the NMOS, and the drain-contact-to-gate-spacing (DCGS) for the PMOS can be smaller than the DCGS for the NMOS.
Public/Granted literature
- US20040245546A1 I/O CELL AND ESD PROTECTION CIRCUIT Public/Granted day:2004-12-09
Information query
IPC分类:
