发明授权
- 专利标题: Method for reducing coefficient of thermal expansion in chip attach packages
- 专利标题(中): 降低芯片连接封装热膨胀系数的方法
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申请号: US10107112申请日: 2002-03-26
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公开(公告)号: US06841026B2公开(公告)日: 2005-01-11
- 发明人: Lawrence Robert Blumberg , Robert Maynard Japp , William John Rudik , John Frank Surowka
- 申请人: Lawrence Robert Blumberg , Robert Maynard Japp , William John Rudik , John Frank Surowka
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: Driggs, Lucas, Brubaker & Hogg Co., LPA
- 代理商 Patrick J. Daugherty
- 主分类号: B32B5/28
- IPC分类号: B32B5/28 ; H05K1/03 ; B32B31/04
摘要:
A simple, inexpensive, drillable, reduced CTE laminate and circuitized structures comprising the reduced CTE laminate, is provided. One embodiment of the reduced CTE laminate comprises: from about 40% to 75%, preferably from about 55% to 65%, by weight resin; from about 0.05% to 0.3%, preferably from about 0.08% to 0.10%, by weight curing agent; from about 25% to 60%, preferably from about 30% to 40%, by weight, woven cloth; from about 1% to 15%, preferably from about 5% to 10%, by volume, non-woven quartz mat. The method for making reduced CTE laminate and laminate structures comprises the following steps: providing non-woven quartz mat; providing a prepreg, preferably B-stage cured to not more than about 40%, preferably not more than 30% of full cure; sandwiching the non-woven quartz mat between two layers of prepreg, and reflowing the resin of the prepreg into the quartz mat.
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