发明授权
US06841441B2 Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealing
有权
用于使用溅射金属沉积,金属离子注入或硅注入的CMOS器件和激光退火的双栅极(一个金属和一个多晶硅或金属硅化物)的制造方法
- 专利标题: Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealing
- 专利标题(中): 用于使用溅射金属沉积,金属离子注入或硅注入的CMOS器件和激光退火的双栅极(一个金属和一个多晶硅或金属硅化物)的制造方法
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申请号: US10338156申请日: 2003-01-08
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公开(公告)号: US06841441B2公开(公告)日: 2005-01-11
- 发明人: Chew Hoe Ang , Eng-Hua Lim , Randall Cher Liang Cha , Jia Zhen Zheng , Elgin Quek , Mei-Sheng Zhou , Daniel Yen
- 申请人: Chew Hoe Ang , Eng-Hua Lim , Randall Cher Liang Cha , Jia Zhen Zheng , Elgin Quek , Mei-Sheng Zhou , Daniel Yen
- 申请人地址: SG Singapore
- 专利权人: Chartered Semiconductor Manufacturing Ltd.
- 当前专利权人: Chartered Semiconductor Manufacturing Ltd.
- 当前专利权人地址: SG Singapore
- 代理机构: Rosemary L. S. Pike
- 代理商 George O Saile; Stephen G. Shanton
- 主分类号: H01L21/268
- IPC分类号: H01L21/268 ; H01L21/28 ; H01L21/8238 ; H01L29/49
摘要:
A method of fabricating first and second gates comprising the following steps. A substrate having a gate dielectric layer formed thereover is provided. The substrate having a first gate region and a second gate region. A thin first gate layer is formed over the gate dielectric layer. The thin first gate layer within the second gate region is masked to expose a portion of the thin first gate layer within the first gate region. The exposed portion of the thin first gate layer is converted to a thin third gate layer portion. A second gate layer is formed over the thin first and third gate layer portions. The second gate layer and the first and third gate layer portions are patterned to form a first gate within first gate region and a second gate within second gate region.
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