发明授权
US06841831B2 Fully-depleted SOI MOSFETs with low source and drain resistance and minimal overlap capacitance using a recessed channel damascene gate process
有权
使用凹陷通道镶嵌栅极工艺，具有低源极和漏极电阻以及最小重叠电容的全耗尽SOI MOSFET
- 专利标题： Fully-depleted SOI MOSFETs with low source and drain resistance and minimal overlap capacitance using a recessed channel damascene gate process
- 专利标题（中）： 使用凹陷通道镶嵌栅极工艺，具有低源极和漏极电阻以及最小重叠电容的全耗尽SOI MOSFET
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申请号： US10461821申请日： 2003-06-13
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公开(公告)号： US06841831B2公开(公告)日： 2005-01-11
- 发明人: Hussein I. Hanafi , Diane C. Boyd , Kevin K. Chan , Wesley Natzle , Leathen Shi
- 申请人： Hussein I. Hanafi , Diane C. Boyd , Kevin K. Chan , Wesley Natzle , Leathen Shi
- 申请人地址： US NY Armonk
- 专利权人： International Business Machines Corporation
- 当前专利权人： International Business Machines Corporation
- 当前专利权人地址： US NY Armonk
- 代理机构： Scully, Scott, Murphy & Presser
- 代理商 Wan Yee Cheung, Esq.
- 主分类号： H01L21/336
- IPC分类号： H01L21/336 ; H01L29/786 ; H01L29/76
摘要：
A sub-0.05 μm channel length fully-depleted SOI MOSFET device having low source and drain resistance and minimal overlap capacitance and a method of fabricating the same are provided. The sub-0.05 μm channel length fully-depleted SOI MOSFET device includes an SOI structure which contains at least an SOI layer having a channel region of a first thickness and abutting source/drain regions of a second thickness present therein, wherein the second thickness is greater than the first thickness and the source/drain regions having a salicide layer present thereon. A gate region is present also atop the SOI layer.