发明授权
US06849549B1 Method for forming dummy structures for improved CMP and reduced capacitance
有权
用于形成用于改善CMP和减小电容的虚拟结构的方法
- 专利标题： Method for forming dummy structures for improved CMP and reduced capacitance
- 专利标题（中）： 用于形成用于改善CMP和减小电容的虚拟结构的方法
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申请号： US10728999申请日： 2003-12-04
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公开(公告)号： US06849549B1公开(公告)日： 2005-02-01
- 发明人: Wen-Chih Chiou , Syun-Ming Jang
- 申请人： Wen-Chih Chiou , Syun-Ming Jang
- 申请人地址： TW Hsin Chu
- 专利权人： Taiwan Semiconductor Manufacturing Co., Ltd
- 当前专利权人： Taiwan Semiconductor Manufacturing Co., Ltd
- 当前专利权人地址： TW Hsin Chu
- 代理机构： Tung & Associates
- 主分类号： H01L21/302
- IPC分类号： H01L21/302 ; H01L21/321 ; H01L21/768
摘要：
A method for forming a damascene structure to improve a chemical mechanical polishing (CMP) process while reducing the capacitance in an integrated circuit including forming a shallow dummy damascene adjacent active damascenes and removing the dummy damascene in a CMP process while forming the adjacent active damascenes.
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