发明授权
- 专利标题： Method for fabricating semiconductor integrated circuit
- 专利标题（中）： 制造半导体集成电路的方法
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申请号： US10453611申请日： 2003-06-04
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公开(公告)号： US06853081B2公开(公告)日： 2005-02-08
- 发明人: Yoshitaka Nakamura , Tsuyoshi Tamaru , Naoki Fukuda , Hidekazu Goto , Isamu Asano , Hideo Aoki , Keizo Kawakita , Satoru Yamada , Katsuhiko Tanaka , Hiroshi Sakuma , Masayoshi Hirasawa
- 申请人： Yoshitaka Nakamura , Tsuyoshi Tamaru , Naoki Fukuda , Hidekazu Goto , Isamu Asano , Hideo Aoki , Keizo Kawakita , Satoru Yamada , Katsuhiko Tanaka , Hiroshi Sakuma , Masayoshi Hirasawa
- 申请人地址： JP Tokyo
- 专利权人： Hitachi, Ltd.
- 当前专利权人： Hitachi, Ltd.
- 当前专利权人地址： JP Tokyo
- 代理机构： Mattingly, Stanger & Malur, P.C.
- 优先权： JP9-174150 19970630
- 主分类号： H01L21/8242
- IPC分类号： H01L21/8242 ; H01L23/522 ; H01L23/48 ; H01L21/44 ; H01L21/4763 ; H01L23/52 ; H01L29/40
摘要：
The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and TiN film 71 on the silicon oxide film 64 are etched back to leave only the inside of the via-hole 66 and form a plug 73. Then, a TiN film 74, Al-alloy film 75, and Ti film 76 are deposited on the silicon oxide film 64 including the surface of the plug 73 by the sputtering method and thereafter, the Ti film 76, Al-alloy film 75, and TiN film 74 are patterned to form second-layer wirings 77 and 78.
公开/授权文献
- US20030205811A1 Method for fabricating semiconductor integrated circuit 公开/授权日：2003-11-06
信息查询
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