- 专利标题: Fully-hidden refresh dynamic random access memory
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申请号: US10352218申请日: 2003-01-28
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公开(公告)号: US06859415B2公开(公告)日: 2005-02-22
- 发明人: Takafumi Takatsuka , Hirotoshi Sato , Masaki Tsukude
- 申请人: Takafumi Takatsuka , Hirotoshi Sato , Masaki Tsukude
- 申请人地址: JP Tokyo
- 专利权人: Renesas Technology Corp.
- 当前专利权人: Renesas Technology Corp.
- 当前专利权人地址: JP Tokyo
- 代理机构: McDermott Will & Emery LLP
- 优先权: JP2002-094477 20020329
- 主分类号: G11C11/403
- IPC分类号: G11C11/403 ; G11C11/406 ; G11C11/00
摘要:
A composite gate detects whether an internal array is in a selected state and an internal row activation signal is activated in accordance with a timing relationship between an output signal of the composite gate and an address transition detection signal. When the address transition detection signal is applied, the internal row activation signal is deactivated in accordance with generation timings of delayed restore period signal indicating whether the internal array is in a selected state and of the address transition detection signal to permit the next row access. With such a configuration, the next operation is allowed to start after an internal state is surely restored to an initial state. When the next address transition detection signal is applied during a period of a restoration operation, a column recovery operation, or a refreshing operation, data access is correctly performed without causing data destruction.
公开/授权文献
- US20030185079A1 Fully-hidden refresh dynamic random access memory 公开/授权日:2003-10-02
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