发明授权
- 专利标题： Method for fabricating laminated silicon gate electrode
- 专利标题（中）： 叠层硅栅电极的制造方法
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申请号： US10274570申请日： 2002-10-21
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公开(公告)号： US06861339B2公开(公告)日： 2005-03-01
- 发明人: Chia-Lin Chen , Liang-Gi Yao , Shih-Chang Chen
- 申请人： Chia-Lin Chen , Liang-Gi Yao , Shih-Chang Chen
- 申请人地址： TW Hsin Chu
- 专利权人： Taiwan Semiconductor Manufacturing Co., Ltd
- 当前专利权人： Taiwan Semiconductor Manufacturing Co., Ltd
- 当前专利权人地址： TW Hsin Chu
- 代理机构： Tung & Associates
- 主分类号： H01L21/20
- IPC分类号： H01L21/20 ; H01L21/28 ; H01L21/30 ; H01L29/49 ; H01L29/78 ; H01L21/26
摘要：
Within a method for forming a silicon layer, there is employed at least one sub-layer formed of a higher crystalline silicon material and at least one sub-layer formed of a lower crystalline silicon material. The lower crystalline silicon material is formed employing a hydrogen treatment of the higher crystalline silicon material. The method is particularly useful for forming polysilicon based gate electrodes with enhanced dimensional control and enhanced performance.
公开/授权文献
- US20040077155A1 Method for fabricating laminated silicon gate electrode 公开/授权日：2004-04-22
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