发明授权
- 专利标题： Semiconductor process using delay-compensated exposure
- 专利标题（中）： 使用延迟补偿曝光的半导体工艺
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申请号： US10274081申请日： 2002-10-21
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公开(公告)号： US06866974B2公开(公告)日： 2005-03-15
- 发明人: Keeho Kim , Jarvis B. Jacobs , Reima T. Laaksonen
- 申请人： Keeho Kim , Jarvis B. Jacobs , Reima T. Laaksonen
- 申请人地址： US TX Dallas
- 专利权人： Texas Instruments Incorporated
- 当前专利权人： Texas Instruments Incorporated
- 当前专利权人地址： US TX Dallas
- 代理商 W. James Brady, III; Frederick J. Telecky, Jr.
- 主分类号： G03B27/00
- IPC分类号： G03B27/00 ; G03F9/00
摘要：
A method of providing critical dimension (CD) gate control during photolithography is achieved by scanning a trial wafer from a batch by an exposure tool and then measuring the gate width to determine shot zones for bi-shot (BSE) exposure. The time delay based on shot or exposure order is determined for each BSE zone. The shot or exposure dose for the other wafers from the same or similar batch is then determined on the bi-shot exposure and the shot order.
公开/授权文献
- US20040076896A1 Semiconductor process using delay-compensated exposure 公开/授权日：2004-04-22
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