公开(公告)号：US07560779B2

公开(公告)日：2009-07-14

申请号：US10426454

申请日：2003-04-29

申请人： Mark S. Rodder ,  Jarvis B. Jacobs

发明人： Mark S. Rodder ,  Jarvis B. Jacobs

IPC分类号： H01L27/088

CPC分类号： H01L21/823857 ,  H01L21/823814

摘要： A mixed voltage circuit is formed by providing a substrate (12) having a first region (20) for forming a first device (106), a second region (22) for forming a second device (108) complementary to the first device (106), and a third region (24) for forming a third device (110) that operates at a different voltage than the first device (106). A gate layer (50) is formed outwardly of the first, second, and third regions (20, 22, 24). While maintaining a substantially uniform concentration of a dopant type (51) in the gate layer (50), a first gate electrode (56) is formed in the first region (20), a second gate electrode (58) is formed in the second region (22), and a third gate electrode (60) is formed in the third region (24). The third region (24) is protected while implanting dopants (72) into the first region (20) to form source and drain features (74) for the first device (106). The first region (20) is protected while implanting dopants (82) into the third region (24) to form disparate source and drain features (84) for the third device (110).

摘要翻译： 通过提供具有用于形成第一装置（106）的第一区域（20）的基板（12），形成与第一装置（106）互补的第二装置（108）的第二区域（22）形成混合电压电路 ）和用于形成在与第一装置（106）不同的电压下工作的第三装置（110）的第三区域（24）。 栅极层（50）形成在第一，第二和第三区域（20,22,24）的外侧。 在栅极层（50）中保持掺杂剂类型（51）的浓度基本均匀的同时，在第一区域（20）中形成第一栅电极（56），第二栅电极（58）形成在第二栅极 区域（22）和第三栅电极（60）形成在第三区域（24）中。 第三区域（24）被保护，同时将掺杂剂（72）注入到第一区域（20）中以形成用于第一装置（106）的源极和漏极特征（74）。 第一区域（20）被保护，同时将掺杂剂（82）注入到第三区域（24）中以形成用于第三装置（110）的不同的源极和漏极特征（84）。

公开(公告)号：US07569464B2

公开(公告)日：2009-08-04

申请号：US11615187

申请日：2006-12-22

申请人： Karen H. R. Kirmse ,  Yuanning Chen ,  Jarvis B. Jacobs ,  Deborah J. Riley

发明人： Karen H. R. Kirmse ,  Yuanning Chen ,  Jarvis B. Jacobs ,  Deborah J. Riley

IPC分类号： H01L21/425

CPC分类号： H01L21/823468 ,  H01L21/823418 ,  H01L21/823814 ,  H01L21/823864

摘要： The present invention provides a method for manufacturing a semiconductor device, which includes forming a gate structure over a substrate, and forming a stack of layers on the substrate and at least partially along a sidewall of the gate structure. In this embodiment, the stack of layers includes an initial layer located over the substrate, a buffer layer located over the initial layer and an offset layer located over the buffer layer. This embodiment of the method further includes removing horizontal segments of the offset layer and the buffer layer using a dry etch and a wet clean, wherein removing includes choosing at least one of an initial thickness of the buffer layer, a period of time for the dry etch or a period of time for the wet clean such that horizontal segments of the initial layer are exposed and substantially unaffected after the dry etch and wet clean.

摘要翻译： 本发明提供了一种制造半导体器件的方法，其包括在衬底上形成栅极结构，并且在衬底上至少部分地沿着栅极结构的侧壁形成层叠层。 在该实施例中，层叠层包括位于衬底上的初始层，位于初始层之上的缓冲层和位于缓冲层上方的偏移层。 该方法的该实施例还包括使用干蚀刻和湿清洁来去除偏移层和缓冲层的水平段，其中移除包括选择缓冲层的初始厚度中的至少一个，干燥时间 蚀刻或湿式清洁的时间段，使得初始层的水平段在干蚀刻和湿清洁之后暴露并基本上不受影响。

公开(公告)号：US20120028431A1

公开(公告)日：2012-02-02

申请号：US13101860

申请日：2011-05-05

申请人： Hiroaki Niimi ,  Jarvis B. Jacobs ,  Reima Tapani Laaksonen

发明人： Hiroaki Niimi ,  Jarvis B. Jacobs ,  Reima Tapani Laaksonen

IPC分类号： H01L21/336

CPC分类号： H01L21/28158 ,  H01L21/28202 ,  H01L21/28247 ,  H01L21/823857 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： The present invention provides a method for forming a semiconductor device, as well as a semiconductor device. The method for manufacturing a semiconductor device, among others, includes providing a gate structure (240) over a substrate (210), the gate structure (240) including a gate electrode (248) located over a nitrided gate dielectric (243), and forming a nitrided region (310) over a sidewall of the nitrided gate dielectric (243).

摘要翻译： 本发明提供一种形成半导体器件的方法以及半导体器件。 制造半导体器件的方法尤其包括在衬底（210）上提供栅极结构（240），所述栅极结构（240）包括位于氮化栅极电介质（243）上方的栅电极（248），以及 在氮化栅极电介质（243）的侧壁上形成氮化区（310）。

公开(公告)号：US20080153273A1

公开(公告)日：2008-06-26

申请号：US11615187

申请日：2006-12-22

申请人： Karen H.R. Kirmse ,  Yuanning Chen ,  Jarvis B. Jacobs ,  Deborah J. Riley

发明人： Karen H.R. Kirmse ,  Yuanning Chen ,  Jarvis B. Jacobs ,  Deborah J. Riley

IPC分类号： H01L21/425

CPC分类号： H01L21/823468 ,  H01L21/823418 ,  H01L21/823814 ,  H01L21/823864

摘要： The present invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, in one embodiment, includes forming a gate structure over a substrate, and forming a stack of layers on the substrate and at least partially along a sidewall of the gate structure. In this embodiment, the stack of layers includes an initial layer located over the substrate, a buffer layer located over the initial layer and an offset layer located over the buffer layer. This embodiment of the method further includes removing horizontal segments of the offset layer and the buffer layer using a dry etch and a wet clean, wherein removing includes choosing at least one of an initial thickness of the buffer layer, a period of time for the dry etch or a period of time for the wet clean such that horizontal segments of the initial layer are exposed and substantially unaffected after the dry etch and wet clean.

摘要翻译： 本发明提供一种制造半导体器件的方法。 在一个实施例中，用于制造半导体器件的方法包括在衬底上形成栅极结构，并且在衬底上并且至少部分地沿栅极结构的侧壁形成层叠层。 在该实施例中，层叠层包括位于衬底上的初始层，位于初始层之上的缓冲层和位于缓冲层上方的偏移层。 该方法的该实施例还包括使用干蚀刻和湿清洁来去除偏移层和缓冲层的水平段，其中移除包括选择缓冲层的初始厚度中的至少一个，干燥时间 蚀刻或湿式清洁的时间段，使得初始层的水平段在干蚀刻和湿清洁之后暴露并基本上不受影响。

公开(公告)号：US06762130B2

公开(公告)日：2004-07-13

申请号：US10160197

申请日：2002-05-31

申请人： Reima Tapani Laaksonen ,  Jarvis B. Jacobs

发明人： Reima Tapani Laaksonen ,  Jarvis B. Jacobs

IPC分类号： H01L21302

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28123 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32137

摘要： A method of forming a narrow feature, such as a gate electrode (14) in an integrated circuit is disclosed. A gate layer (14) such as polycrystalline silicon is disposed near a surface of a substrate (12), and a hardmask layer (16) is formed over the gate layer (14). The hardmask layer (16) includes one or more dielectric layers (16a, 16b, 16c) such as silicon-rich silicon nitride, silicon oxynitride, and oxide. Photoresist (18) sensitive to 193 nm UV light is patterned over the hardmask layer (16) to define a feature of a first width (CD) that is reliably patterned at that wavelength. The hardmask layer (16) is then etched to clear from the surface of the gate layer (14). A timed overetch of the hardmask layer (16) reduces hardmask CD and that of the overlying photoresist (18) to the desired feature size. Etch of the gate layer is then carried out to form the desired feature.

摘要翻译： 公开了一种在集成电路中形成诸如栅电极（14）的窄特征的方法。 诸如多晶硅的栅极层（14）设置在衬底（12）的表面附近，并且在栅极层（14）上形成硬掩模层（16）。 硬掩模层（16）包括一个或多个介电层（16a，16b，16c），例如富硅氮化硅，氮氧化硅和氧化物。 对强度为193nm的紫外光敏感的光致抗蚀剂（18）在硬掩模层（16）上图案化以限定在该波长下可靠地图案化的第一宽度（CD）的特征。 然后蚀刻硬掩模层（16）以从栅极层（14）的表面清除。 硬掩模层（16）的定时过蚀刻将硬掩模CD和上覆光致抗蚀剂（18）的硬掩模CD和硬掩模CD降低到所需的特征尺寸。 然后执行栅极层的蚀刻以形成期望的特征。

公开(公告)号：US5936278A

公开(公告)日：1999-08-10

申请号：US813524

申请日：1997-03-07

申请人： Yin Hu ,  Jarvis B. Jacobs ,  Theodore W. Houston

发明人： Yin Hu ,  Jarvis B. Jacobs ,  Theodore W. Houston

IPC分类号： H01L29/73 ,  H01L21/265 ,  H01L21/331 ,  H01L21/336 ,  H01L21/822 ,  H01L27/12 ,  H01L29/10 ,  H01L29/732 ,  H01L29/786 ,  H01L27/01 ,  H01L31/0392

CPC分类号： H01L29/1045 ,  H01L29/66265 ,  H01L29/66772 ,  H01L29/7317 ,  H01L29/78654

摘要： A semiconductor over insulator transistor (100) includes a semiconductor mesa (36) formed over an insulating layer (34) which overlies a semiconductor substrate (32). Source and drain regions (66, 68) of a first conductivity type are formed at opposite ends of the mesa. A body node (56) of a second conductivity type is located between the source and drain regions in the mesa. A gate insulator (40) and a gate electrode (46) lie over the body node. Halo implants (54, 56) are placed to completely separate the source and drain regions from the body node, or channel regions, for improving short channel effect. The transistor is useful as a pass gate and as a peripheral transistor in a DRAM, and also is useful in digital and analog applications and in low power applications.

摘要翻译： 半导体绝缘体晶体管（100）包括形成在覆盖半导体衬底（32）的绝缘层（34）上的半导体台面（36）。 第一导电类型的源区和漏区（66,68）形成在台面的相对端。 第二导电类型的体节点（56）位于台面的源极和漏极区域之间。 门绝缘体（40）和栅电极（46）位于身体节点之上。 放置光晕植入物（54,56）以将源极和漏极区域与体节点或通道区域完全分离，以改善短通道效应。 该晶体管作为通路栅极和作为DRAM中的外围晶体管是有用的，并且在数字和模拟应用以及低功率应用中也是有用的。

公开(公告)号：US08802577B2

公开(公告)日：2014-08-12

申请号：US13101860

申请日：2011-05-05

申请人： Hiroaki Niimi ,  Jarvis B. Jacobs ,  Reima Tapani Laaksonen

发明人： Hiroaki Niimi ,  Jarvis B. Jacobs ,  Reima Tapani Laaksonen

IPC分类号： H01L21/31 ,  H01L21/28

CPC分类号： H01L21/28158 ,  H01L21/28202 ,  H01L21/28247 ,  H01L21/823857 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： The present invention provides a method for forming a semiconductor device, as well as a semiconductor device. The method for manufacturing a semiconductor device, among others, includes providing a gate structure (240) over a substrate (210), the gate structure (240) including a gate electrode (248) located over a nitrided gate dielectric (243), and forming a nitrided region (310) over a sidewall of the nitrided gate dielectric (243).

摘要翻译： 本发明提供一种形成半导体器件的方法以及半导体器件。 制造半导体器件的方法尤其包括在衬底（210）上提供栅极结构（240），所述栅极结构（240）包括位于氮化栅极电介质（243）上方的栅电极（248），以及 在氮化栅极电介质（243）的侧壁上形成氮化区（310）。

公开(公告)号：US06866974B2

公开(公告)日：2005-03-15

申请号：US10274081

申请日：2002-10-21

申请人： Keeho Kim ,  Jarvis B. Jacobs ,  Reima T. Laaksonen

发明人： Keeho Kim ,  Jarvis B. Jacobs ,  Reima T. Laaksonen

IPC分类号： G03B27/00 ,  G03F9/00

CPC分类号： G03B27/00 ,  G03F7/70425

摘要： A method of providing critical dimension (CD) gate control during photolithography is achieved by scanning a trial wafer from a batch by an exposure tool and then measuring the gate width to determine shot zones for bi-shot (BSE) exposure. The time delay based on shot or exposure order is determined for each BSE zone. The shot or exposure dose for the other wafers from the same or similar batch is then determined on the bi-shot exposure and the shot order.

摘要翻译： 在光刻期间提供关键尺寸（CD）栅极控制的方法是通过用曝光工具从批次中扫描试验晶片，然后测量栅极宽度来确定双击（BSE）曝光的拍摄区域来实现的。 针对每个BSE区域确定基于拍摄或曝光顺序的时间延迟。 然后从双相曝光和拍摄顺序确定来自相同或相似批次的其它晶片的拍摄或曝光剂量。

公开(公告)号：US06583013B1

公开(公告)日：2003-06-24

申请号：US09452037

申请日：1999-11-30

申请人： Mark S. Rodder ,  Jarvis B. Jacobs

发明人： Mark S. Rodder ,  Jarvis B. Jacobs

IPC分类号： H01L218236

CPC分类号： H01L21/823814 ,  H01L21/823857

摘要： A mixed voltage circuit is formed by providing a substrate (12) having a first region (20) for forming a first device (106), a second region (22) for forming a second device (108) complementary to the first device (106), and a third region (24) for forming a third device (110) that operates at a different voltage than the first device (106). A gate layer (50) is formed outwardly of the first, second, and third regions (20, 22, 24). While maintaining a substantially uniform concentration of a dopant type (51) in the gate layer (50), a first gate electrode (56) is formed in the first region (20), a second gate electrode (58) is formed in the second region (22), and a third gate electrode (60) is formed in the third region (24). The third region (24) is protected while implanting dopants (72) into the first region (20) to form source and drain features (74) for the first device (106). The first region (20) is protected while implanting dopants (82) into the third region (24) to form disparate source and drain features (84) for the third device (110).