Invention Grant
US06870273B2 High speed I/O pad and pad/cell interconnection for flip chips
有权
用于倒装芯片的高速I / O焊盘和焊盘/单元互连
- Patent Title: High speed I/O pad and pad/cell interconnection for flip chips
- Patent Title (中): 用于倒装芯片的高速I / O焊盘和焊盘/单元互连
-
Application No.: US10424817Application Date: 2003-04-29
-
Publication No.: US06870273B2Publication Date: 2005-03-22
- Inventor: Yuming Tao , Vernon R. Little
- Applicant: Yuming Tao , Vernon R. Little
- Applicant Address: CA
- Assignee: PMC-Sierra, Inc.
- Current Assignee: PMC-Sierra, Inc.
- Current Assignee Address: CA
- Agent Clifford W. Vermette
- Main IPC: H01L21/60
- IPC: H01L21/60 ; H01L23/50 ; H01L23/528 ; H01L23/552 ; H01L23/48
Abstract:
Gridded I/O pads for flip-chip packages in which a coaxial-like solder bump pad configuration is used in which the I/O pads closest to the signal or bump pad are power or ground pads. The ground pads surrounding the signal pad form a coaxial-like pad configuration for impedance matching at the transition from die to package substrate. The ground pads surrounding the signal pad may be connected by a metal trace to form a ground pad ring. The invention employs conductor-backed ground coplanar waveguides (GCPW), which match impedance at connections between I/O cells and signal pads to enhance signal transmission, avoid reflection and leakage, and provide superior electromagnetic shielding. The present invention also supports high quantities of I/Os for a given die size, and supports flexible power and ground placement.
Public/Granted literature
- US20040026794A1 High speed I/O pad and pad/cell interconnection for flip chips Public/Granted day:2004-02-12
Information query
IPC分类:
