公开(公告)号：US5537055A

公开(公告)日：1996-07-16

申请号：US269083

申请日：1994-06-30

Applicant: Graham B. Smith ,  Charles K. Huscroft ,  Vernon R. Little

Inventor： Graham B. Smith ,  Charles K. Huscroft ,  Vernon R. Little

IPC: H03K19/003 ,  H04L9/00

CPC classification number: H03K19/003

Abstract: A design protection circuit for a logic circuit comprised of a counter for receiving clock pulses with the logic circuit and apparatus for resetting the logic circuit upon the counter counting a predetermined number of clock pulses, the predetermined number being higher than a highest number of clock pulses required by the logic circuit for carrying out a simulated logical function.

Abstract translation: 一种用于逻辑电路的设计保护电路，包括用于接收具有逻辑电路的时钟脉冲的计数器和用于在计数器对计数预定数量的时钟脉冲时复位逻辑电路的装置，该预定数目高于最高数量的时钟脉冲 逻辑电路需要用于执行模拟逻辑功能。

公开(公告)号：US5461621A

公开(公告)日：1995-10-24

申请号：US251958

申请日：1994-06-01

Applicant: Vernon R. Little

Inventor： Vernon R. Little

IPC: H04J3/07 ,  H04J3/22 ,  H04L7/027 ,  H04L25/14

CPC classification number: H04L25/14

Abstract: For use in a transmission system in which an input data stream is transmitted in plural data streams each at a fraction of the input data stream rate and plural clock stream pairs each at the fraction of the input data clock rate, a receiver, comprised of apparatus for receiving the plural data streams, apparatus for determining frame timing differences between frame signals contained in each of the received plural data streams, apparatus for varying the timing of one received data stream relates to another, whereby their relative timing is adjusted, apparatus for combining the timing adjusted plural data streams into an output data stream having a similar data stream rate as the input data stream, apparatus for recovering a clock from one of the plural data streams, and for generating an output clock signal therefrom at the input data clock rate, and apparatus for aligning the output data stream with the output clock signal, whereby an output data stream and an output clock signal are provided having similar data rates as the input data stream and clock rates.

Abstract translation: 对于其中输入数据流以多个输入数据流速率的一部分和多个时钟流对以多个数据流发送的传输系统中的每一个以输入数据时钟速率的一部分传输的传输系统，包括设备 为了接收多个数据流，用于确定包含在接收到的多个数据流中的每一个的帧信号之间的帧定时差的装置，用于改变一个接收数据流的定时的装置与另一个接收的数据流的定时相关，由此调整其相对定时， 定时将多个数据流调整为具有与输入数据流类似的数据流速率的输出数据流，用于从多个数据流中的一个数据流恢复时钟的装置，并且用于以输入数据时钟速率从其产生输出时钟信号 以及用于将输出数据流与输出时钟信号对准的装置，由此输出数据流和输出时钟信号是 提供与输入数据流和时钟速率相似的数据速率。

公开(公告)号：US6088369A

公开(公告)日：2000-07-11

申请号：US865736

申请日：1997-05-30

Applicant: Stephen Dabecki ,  Brian Gerson ,  Barry Hagglund ,  Charles Kevin Huscroft ,  Vernon R. Little

Inventor： Stephen Dabecki ,  Brian Gerson ,  Barry Hagglund ,  Charles Kevin Huscroft ,  Vernon R. Little

IPC: H04L25/49 ,  H04J3/06

CPC classification number: H04L25/4917

Abstract: According to the invention there is provided a method of signal coding that permits high speed data transmission over multiple pairs of UTP-5 cable from a transmission end to a receiving end which includes, at the transmission end, separating an incoming frame of data into a plurality of byte streams with a predefined sequence of bytes assigned to each of the streams, encoding every 2 bits of data in each stream into one of 4 logical voltage levels forming a symbol or quat thereby reducing the symbol or baud rate by 50% and inserting an escape sequence into one or more of the streams consisting of a sequence of zero's followed by a control code to indicate a transition from one state to another. At a receiving end, the method further includes reading the escape sequence and decoding the signals in accordance with the code contained in the escape sequence.

Abstract translation: 根据本发明，提供了一种信号编码方法，其允许从传输端到接收端的多对UTP-5电缆的高速数据传输，所述UTP-5电缆在传输端包括将输入的数据帧分离成 具有分配给每个流的预定义字节序列的多个字节流，将每个流中的每2位数据编码为形成符号或四进制的4个逻辑电压电平之一，从而将符号或波特率减少50％并插入 将一个或多个流中的一个或多个流的转义序列组成为一个零序列，随后是一个控制代码，以指示从一个状态到另一个状态的转换。 在接收端，该方法还包括读取转义序列并根据转义序列中包含的代码对信号进行解码。

公开(公告)号：US07492714B1

公开(公告)日：2009-02-17

申请号：US10771268

申请日：2004-02-03

Applicant: Heng Liao ,  Stacy Nichols ,  Vernon R Little ,  Kevin Huscroft

Inventor： Heng Liao ,  Stacy Nichols ,  Vernon R Little ,  Kevin Huscroft

IPC: G01R31/08 ,  H04L12/28

CPC classification number: H04L12/4604 ,  H04L45/742 ,  H04L47/10 ,  H04L47/2441 ,  H04L47/32

Abstract: A method and apparatus for building a packet grooming and aggregation engine is disclosed. The grooming and aggregation engine can be applied to the network for providing flexible aggregation and service multiplexing functions. A method and apparatus achieves the intended function that is easy to implement and easy for the network operator to manage, yet provides enough flexibility to mix and match various services at the edge node of the network. One specific embodiment of the patent is an Ethernet over SONET mapping system where user traffic is aggregated and groomed into SONET transport virtual concatenation channels.

Abstract translation: 公开了一种构建分组整理和聚合引擎的​​方法和装置。 整理和聚合引擎可以应用于网络，提供灵活的聚合和业务复用功能。 一种方法和装置实现了易于实现和易于网络运营商管理的预期功能，但是提供足够的灵活性来混合和匹配网络边缘节点处的各种服务。 该专利的一个具体实施例是SONET映射系统以太网，其中用户业务被聚合并整合到SONET传输虚拟级联信道中。

公开(公告)号：US06870273B2

公开(公告)日：2005-03-22

申请号：US10424817

申请日：2003-04-29

Applicant: Yuming Tao ,  Vernon R. Little

Inventor： Yuming Tao ,  Vernon R. Little

IPC: H01L21/60 ,  H01L23/50 ,  H01L23/528 ,  H01L23/552 ,  H01L23/48

CPC classification number: H01L24/81 ,  H01L23/50 ,  H01L23/5286 ,  H01L23/552 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2223/6638 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/16225 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/15311 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014

Abstract: Gridded I/O pads for flip-chip packages in which a coaxial-like solder bump pad configuration is used in which the I/O pads closest to the signal or bump pad are power or ground pads. The ground pads surrounding the signal pad form a coaxial-like pad configuration for impedance matching at the transition from die to package substrate. The ground pads surrounding the signal pad may be connected by a metal trace to form a ground pad ring. The invention employs conductor-backed ground coplanar waveguides (GCPW), which match impedance at connections between I/O cells and signal pads to enhance signal transmission, avoid reflection and leakage, and provide superior electromagnetic shielding. The present invention also supports high quantities of I/Os for a given die size, and supports flexible power and ground placement.

Abstract translation: 用于倒装芯片封装的栅格I / O焊盘，其中使用最接近信号或凸块焊盘的I / O焊盘的同轴式焊料凸块焊盘配置是电源或接地焊盘。 围绕信号焊盘的接地焊盘形​​成同轴状的焊盘配置，用于在从芯片到封装基板的过渡处的阻抗匹配。 信号焊盘周围的接地焊盘可以通过金属迹线连接以形成接地焊盘环。 本发明采用导体背面的共面波导（GCPW），其与I / O单元和信号焊盘之间的连接处的阻抗匹配，以增强信号传输，避免反射和泄漏，并提供卓越的电磁屏蔽。 本发明还支持用于给定裸片尺寸的大量I / O，并且支持灵活的电源和接地放置。

公开(公告)号：US06188692B1

公开(公告)日：2001-02-13

申请号：US09022489

申请日：1998-02-12

Applicant: Charles K. Huscroft ,  John R. Bradshaw ,  Vernon R. Little ,  Brian D. Gerson ,  Graham B. Smith

Inventor： Charles K. Huscroft ,  John R. Bradshaw ,  Vernon R. Little ,  Brian D. Gerson ,  Graham B. Smith

IPC: H04J307

CPC classification number: H04Q11/0478 ,  H04J3/1617 ,  H04L2012/5614 ,  H04L2012/5653

Abstract: A user network interface device for interfacing between synchronous optical network (SONET)/synchronous digital hierarchy (SDH) which is characterized by a continuous stream of frames of data and an asynchronous transfer mode (ATM) characterized by a non-continuous stream of cells of data. The user network interface device includes an integral phase lock loop circuit to recover clock and data from an encoded incoming stream of data. In another embodiment, the network interface device synthesizes a high speed transmit clock from a low frequency reference source.

Abstract translation: 一种用于在同步光网络（SONET）/同步数字分层（SDH）之间进行接口的用户网络接口设备，其特征在于连续的数据帧流和异步传输模式（ATM），其特征在于非连续流的小区 数据。 用户网络接口设备包括整体锁相环电路，用于从编码的输入数据流中恢复时钟和数据。 在另一个实施例中，网络接口设备从低频参考源合成高速发射时钟。

公开(公告)号：US5568486A

公开(公告)日：1996-10-22

申请号：US250895

申请日：1994-05-31

Applicant: Charles K. Huscroft ,  David W. Wong ,  Steven F. Lang ,  Vernon R. Little

Inventor： Charles K. Huscroft ,  David W. Wong ,  Steven F. Lang ,  Vernon R. Little

IPC: H04J3/06 ,  H04L7/04 ,  H04L12/70 ,  H04J3/07

CPC classification number: H04Q11/0478 ,  H04J3/0608 ,  H04J3/1617 ,  H04L2012/5616 ,  H04L2012/5652 ,  H04L2012/5672 ,  H04L7/048

Abstract: A method of interfacing between a non-continuous stream of cells of data and a continuous stream of frames of data, which includes transforming an incoming non-continuous cell stream into a continuous transmitted stream by inserting idle or non-assigned cells into the data stream during idle periods. The cells in the continuous stream are then mapped sequentially and contiguously onto the payload portions of frames. The frames are then transmitted synchronously.

Abstract translation: 一种在不连续的数据信元流与连续的数据帧流之间进行接口的方法，其包括通过将空闲或未分配的小区插入数据流来将输入的非连续小区流变换为连续的发送流 在空闲期间。 然后将连续流中的小区顺序地并且连续地映射到帧的有效载荷部分上。 然后帧被同步传输。