Invention Grant
US06873013B2 Silicon-on-insulator structure and method of reducing backside drain-induced barrier lowering
失效
绝缘体上的结构和减少背面漏极引起的屏障降低的方法
- Patent Title: Silicon-on-insulator structure and method of reducing backside drain-induced barrier lowering
- Patent Title (中): 绝缘体上的结构和减少背面漏极引起的屏障降低的方法
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Application No.: US10396950Application Date: 2003-03-24
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Publication No.: US06873013B2Publication Date: 2005-03-29
- Inventor: Brian Roberds , Doulgas W. Barlage
- Applicant: Brian Roberds , Doulgas W. Barlage
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L29/45 ; H01L29/49 ; H01L29/786 ; H01L27/01
Abstract:
The invention relates to a transistor that includes a semiconductive layer on an insulator layer. Below the insulator layer is a substrate and a contact is disposed in the insulator layer that originates at the substrate and terminates in the insulator layer. The contact is aligned below the transistor junction. The invention also relates to a process flow that is used to fabricate the transistor. The process flow includes forming the contact by either a spacer etch or a directional, angular etch.
Public/Granted literature
- US20030178680A1 Silicon-on-insulator structure and method of reducing backside drain-induced barrier lowering Public/Granted day:2003-09-25
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