Invention Grant
US06880049B2 Sharing a second tier cache memory in a multi-processor 有权
在多处理器中共享第二层高速缓存

Sharing a second tier cache memory in a multi-processor
Abstract:
A set of cache memory includes a set of first tier cache memory and a second tier cache memory. In the set of first tier cache memory each first tier cache memory is coupled to a compute engine in a set of compute engines. The second tier cache memory is coupled to each first tier cache memory in the set of first tier cache memory. The second tier cache memory includes a data ring interface and a snoop ring interface.
Public/Granted literature
Information query
Patent Agency Ranking
0/0