利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

30 条记录 (耗时 0.029 秒)

    Advanced processor with mechanism for maximizing resource usage in an in-order pipeline with multiple threads
    3.
    发明申请
    Advanced processor with mechanism for maximizing resource usage in an in-order pipeline with multiple threads 审中-公开
    具有最大化具有多个线程的按顺序管道中的资源使用的机制的高级处理器

    公开(公告)号：US20050044324A1

    公开(公告)日：2005-02-24

    申请号：US10930939

    申请日：2004-08-31

    申请人： Abbas Rashid ,  David Hass

    发明人： Abbas Rashid ,  David Hass

    IPC分类号： G06F12/08 ,  H04L12/56 ,  G06F12/14 ,  G06F13/00

    CPC分类号： H04L49/00 ,  G06F12/0813 ,  H04L49/15

    摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

    摘要翻译： 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

    Advanced processor with mechanism for packet distribution at high line rate
    4.
    发明申请
    Advanced processor with mechanism for packet distribution at high line rate 失效
    高级处理器，具有高线速率的数据包分发机制

    公开(公告)号：US20050027793A1

    公开(公告)日：2005-02-03

    申请号：US10931014

    申请日：2004-08-31

    申请人： David Hass

    发明人： David Hass

    IPC分类号： G06F12/08 ,  H04L12/56 ,  G06F15/16

    CPC分类号： H04L49/15 ,  G06F12/0813

    摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

    摘要翻译： 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

    Microcomputer controlled faucet
    5.
    发明授权
    Microcomputer controlled faucet 失效
    微电脑控制龙头

    公开(公告)号：US4931938A

    公开(公告)日：1990-06-05

    申请号：US837500

    申请日：1986-03-07

    申请人： David Hass

    发明人： David Hass

    IPC分类号： G05D23/13

    CPC分类号： G05D23/1393

    摘要： A faucet supplies water at a computer controlled temperture. Hot and cold water valves are connected to hot and cold water supplies. A mixing connection is attached between the valves for mixing the hot and cold water together and supplying it at a faucet discharge. Each valve has a movable valve member which can be moved toward and away from a valve seat to control the flow of hot or cold water. A stepper motor is connected to each of the valve members and can be controlled by a digital error signal to rotate, in steps, either to increase or decrease the flow of hot or cold water. A temperature sensor is provided at the faucet outlet for sensing the actual temperature. A microcomputer receives signals corresponding to the actual temperature. The actual temperature is compared to a selected set point temperature which is programmed into the microcomputer. If an error exists between the actual and set point temperatures, control signals are supplied to the stepper motors for changing the flow of hot or cold water to move the actual temperature toward the set point temperature.

    摘要翻译： 水龙头在计算机控制的温度下供水。 冷热水阀门连接冷热水供应。 在阀之间连接有混合连接件，用于将热水和冷水混合在一起并在水龙头排放处供应。 每个阀具有可移动的阀构件，其可以朝向和远离阀座移动以控制热水或冷水的流动。 步进电动机连接到每个阀构件，并且可以通过数字误差信号来控制，以逐步旋转以增加或减少热水或冷水的流动。 在水龙头出口处设有温度传感器，用于感测实际温度。 微型计算机接收与实际温度相对应的信号。 将实际温度与编程到微型计算机中的选定设定点温度进行比较。 如果在实际温度和设定温度之间存在误差，则将控制信号提供给步进电机，以改变热水或冷水的流量，以将实际温度向设定点温度移动。

    Advanced processor translation lookaside buffer management in a multithreaded system
    6.
    发明申请
    Advanced processor translation lookaside buffer management in a multithreaded system 失效
    多线程系统中的高级处理器转换后备缓冲区管理

    公开(公告)号：US20070204130A1

    公开(公告)日：2007-08-30

    申请号：US11704709

    申请日：2007-02-08

    申请人： David Hass ,  Basab Mukherjee

    发明人： David Hass ,  Basab Mukherjee

    IPC分类号： G06F12/00

    CPC分类号： G06F12/1036 ,  G06F12/0813 ,  H04L49/00

    摘要： Advanced processors for executing software applications on different operating system are presented including: a number of processor cores each configured to execute multiple threads, wherein each of the number of processor cores includes a data cache and an instruction cache; a data switch interconnect ring arrangement directly coupled with the data cache of each of the number of processor cores and configured to pass memory related information among the number of processor cores; a messaging network directly coupled with the instruction cache of each of the number of processor cores and a number of communication ports; and a memory management unit (MMU) coupled with each of the number of processor cores, the MMU having a first translation-lookaside buffer (TLB) portion, a second TLB portion, and a third TLB portion, wherein each TLB portion is operable in several modes, wherein each TLB portion includes a number of entries.

    摘要翻译： 提出了用于在不同操作系统上执行软件应用的高级处理器，包括：多个处理器核，每个被配置为执行多个线程，其中每个处理器核心包括数据高速缓存和指令高速缓存; 数据交换互连环布置，与所述多个处理器核心中的每一个的数据高速缓存直接耦合，并且被配置为在所述多个处理器核之间传递存储器相关信息; 直接与多个处理器核心中的每一个的指令高速缓存和多个通信端口耦合的消息传递网络; 以及与所述多个处理器核心中的每一个耦合的存储器管理单元（MMU），所述MMU具有第一翻译后视缓冲器（TLB）部分，第二TLB部分和第三TLB部分，其中每个TLB部分可操作 几种模式，其中每个TLB部分包括多个条目。

    Advanced processor with implementation of memory ordering on a ring based data movement network
    7.
    发明申请
    Advanced processor with implementation of memory ordering on a ring based data movement network 失效
    在基于环的数据移动网络上实现存储器排序的高级处理器

    公开(公告)号：US20060056290A1

    公开(公告)日：2006-03-16

    申请号：US10930187

    申请日：2004-08-31

    申请人： David Hass

    发明人： David Hass

    IPC分类号： H04L12/26

    CPC分类号： H04L47/624 ,  H04L47/24 ,  H04L47/50 ,  H04L47/568 ,  H04L49/90 ,  H04L49/9094

    摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

    摘要翻译： 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

    First tier cache memory preventing stale data storage
    8.
    发明授权
    First tier cache memory preventing stale data storage 有权
    第一层缓存内存可防止过时的数据存储

    公开(公告)号：US06862669B2

    公开(公告)日：2005-03-01

    申请号：US10105732

    申请日：2002-03-25

    申请人： Fred Gruner ,  David Hass ,  Robert Hathaway

    发明人： Fred Gruner ,  David Hass ,  Robert Hathaway

    IPC分类号： G06F12/00 ,  G06F12/08 ,  H04L12/56 ,  G06F13/00

    CPC分类号： H04L47/10 ,  G06F12/0813 ,  G06F12/0831 ,  G06F12/084 ,  H04L47/12 ,  H04L47/20 ,  H04L47/2441 ,  H04L47/765 ,  H04L47/805 ,  H04L47/822

    摘要： An apparatus includes a compute engine coupled to a first tier cache memory including a data array. The first tier cache receives memory access requests from the compute engine. A second tier cache memory is coupled to the first tier cache to receive memory access requests for memory locations not owned by the first tier cache. To avoid stale data storage, the first tier cache does not load the data array with data returned by the second tier cache under the following condition—the second tier cache returns the data in response to a cacheable load operation from a memory location after the compute engine issues a subsequent store operation to the same memory location.

    摘要翻译： 一种装置包括耦合到包括数据阵列的第一层高速缓冲存储器的计算引擎。 第一层缓存从计算引擎接收内存访问请求。 第二层缓存存储器耦合到第一层高速缓存以接收对于不是由第一层高速缓存拥有的存储器位置的存储器访问请求。 为了避免陈旧的数据存储，第一层缓存不会在以下条件下加载数据数组，数据由第二层缓存返回的数据 - 第二层缓存响应于计算后的内存位置的可缓存加载操作而返回数据 引擎将后续的存储操作发送到相同的存储器位置。

    Advanced processor with out of order load store scheduling in an in order pipeline
    9.
    发明申请
    Advanced processor with out of order load store scheduling in an in order pipeline 有权
    先进的处理器，按顺序流水线排序加载存储调度

    公开(公告)号：US20050044323A1

    公开(公告)日：2005-02-24

    申请号：US10930938

    申请日：2004-08-31

    申请人： David Hass

    发明人： David Hass

    IPC分类号： G06F12/08 ,  H04L12/56 ,  G06F12/14 ,  G06F13/28

    CPC分类号： H04L49/00 ,  G06F12/0813 ,  H04L49/90

    摘要： An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

    摘要翻译： 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

    Speculative renaming of data-processor registers
    10.
    发明授权
    Speculative renaming of data-processor registers 有权
    将虚拟寄存器规范映射到流水线处理器中的物理寄存器

    公开(公告)号：US06591359B1

    公开(公告)日：2003-07-08

    申请号：US09223843

    申请日：1998-12-31

    申请人： David Hass ,  Michael P. Corwin ,  Luke E. Girard ,  Ken Arora ,  Harshvardhan Sharangpani ,  Syed Reza

    发明人： David Hass ,  Michael P. Corwin ,  Luke E. Girard ,  Ken Arora ,  Harshvardhan Sharangpani ,  Syed Reza

    IPC分类号： G06F934

    CPC分类号： G06F9/3863 ,  G06F9/384 ,  G06F9/3842

    摘要： A pipelined data processor has instructions at different stages of execution. Some of the instructions specify virtual addresses into a file of registers having physical addresses. A speculative translator maps the virtual registers of an instruction at one pipeline stage into physical registers for speculative use by the instruction at a later pipeline stage. The registers have multiple differently translated regions. Failure of speculative renaming reverts to an archive copy of renaming data.

    摘要翻译： 流水线数据处理器具有不同执行阶段的指令。 一些指令将虚拟地址指定为具有物理地址的寄存器的文件。 推测翻译器将一个流水线阶段的指令的虚拟寄存器映射到物理寄存器，以便在稍后的流水线阶段由指令进行投机使用。 寄存器有多个不同的翻译区域。 投机重命名失败恢复到重命名数据的归档副本。