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发明授权
US06898694B2 High instruction fetch bandwidth in multithread processor using temporary instruction cache to deliver portion of cache line in subsequent clock cycle 有权
多线程处理器中的高指令提取带宽使用临时指令高速缓存在随后的时钟周期内传送部分高速缓存行

High instruction fetch bandwidth in multithread processor using temporary instruction cache to deliver portion of cache line in subsequent clock cycle
摘要：
The present invention provides a mechanism for supporting high bandwidth instruction fetching in a multi-threaded processor. A multi-threaded processor includes an instruction cache (I-cache) and a temporary instruction cache (TIC). In response to an instruction pointer (IP) of a first thread hitting in the I-cache, a first block of instructions for the thread is provided to an instruction buffer and a second block of instructions for the thread are provided to the TIC. On a subsequent clock interval, the second block of instructions is provided to the instruction buffer, and first and second blocks of instructions from a second thread are loaded into a second instruction buffer and the TIC, respectively.
摘要（中）：

本发明提供一种用于在多线程处理器中支持高带宽指令提取的机制。 多线程处理器包括指令高速缓存（I-cache）和临时指令高速缓存（TIC）。 响应于在I缓存中击中的第一线程的指令指针（IP），将线程的第一指令块提供给指令缓冲器，并且向TIC提供用于线程的第二指令块。 在随后的时钟间隔中，第二指令块被提供给指令缓冲器，并且来自第二线程的第一和第二指令块分别被加载到第二指令缓冲器和TIC中。

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