Invention Grant
US06901106B1 Delay lock code tracking loop employing multiple timing references 有权
延迟锁定码跟踪循环采用多个定时参考

Delay lock code tracking loop employing multiple timing references
Abstract:
A code tracking system and method especially for use in direct sequence code division multiple access (DS-CDMA) communication systems employs multiple timing references within a chip by tracking the multiple timing references relative to the exact midpoint of the chip, then adjusting the timing references to the exact midpoint of the chip, and outputting an error tracking signal in accordance with the minimum error associated with the multiple timing references. The system performs effective code tracking with low lock-loss rate even when the noise of a receiving path interferes with detection of some of the timing references. The system uses multiple delay-locked loops for the different timing references.
Information query
Patent Agency Ranking
0/0