Disclosed is a method for fabricating a silicide layer of a flat cell memory device. The disclosed method comprises the steps of: providing a silicon substrate whereon a flat cell array region and a peripheral circuit region are defined; forming a word line and a bit diffusion layer on the flat cell array region of the substrate and a word line and source/drain junction on the peripheral circuit region; forming a gap fill insulating layer to fill up the gap between the word lines; removing the gap fill insulating layer on the peripheral circuit region; forming an insulating layer on the whole substrate; dry etching the insulating layer to expose a surface of word line, and a surface of the substrate of the peripheral circuit region, thereby forming a spacer on a side wall of the word line of the peripheral circuit region; and forming a silicide layer on the upper part of the word line of the flat cell array region and, at the same time, forming a salicide layer on the upper part of the word line and the surface of the substrate of the peripheral circuit region.