Invention Grant
US06917105B2 Integrating chip scale packaging metallization into integrated circuit die structures
有权
将芯片级封装金属化集成到集成电路管芯结构中
- Patent Title: Integrating chip scale packaging metallization into integrated circuit die structures
- Patent Title (中): 将芯片级封装金属化集成到集成电路管芯结构中
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Application No.: US10453157Application Date: 2003-06-03
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Publication No.: US06917105B2Publication Date: 2005-07-12
- Inventor: Martin Alter
- Applicant: Martin Alter
- Applicant Address: US CA San Jose
- Assignee: Micrel, Incorporated
- Current Assignee: Micrel, Incorporated
- Current Assignee Address: US CA San Jose
- Agent J. Vincent Tortolano; Eugene H. Valet
- Main IPC: H01L21/60
- IPC: H01L21/60 ; H01L23/31 ; H01L23/485 ; H01L23/48
Abstract:
Wafer-level chip-scale packaging technology is used for improving performance or reducing size of integrated circuits by using metallization of pad-to-bump-out beams as part of the integrated circuit structure. Chip-scale packaging under bump metal is routed to increase the thickness of top metal of the integrated circuit, increasing current carrying capability and reducing resistance. An exemplary embodiment for a power MOSFET array integrated structure is described.
Public/Granted literature
- US20040245631A1 Integrating chip scale packaging metallization into integrated circuit die structures Public/Granted day:2004-12-09
Information query
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