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    SYSTEM FOR VERTICAL DMOS WITH SLOTS
    1.
    发明申请
    SYSTEM FOR VERTICAL DMOS WITH SLOTS 有权
    垂直DMOS系统

    公开(公告)号：US20100065906A1

    公开(公告)日：2010-03-18

    申请号：US12622360

    申请日：2009-11-19

    Applicant: Martin ALTER ,  John Durbin HUSHER

    Inventor： Martin ALTER ,  John Durbin HUSHER

    IPC: H01L29/78

    CPC classification number: H01L21/743 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/4925 ,  H01L29/7809 ,  H01L29/7813

    Abstract: A device for providing a high power, low resistance, efficient vertical DMOS device is disclosed. The device comprises providing a semiconductor substrate with a source body structure thereon. The device further comprises a plurality of slots in the source/body structure and providing a metal within the plurality of slots to form a plurality of structures. A slotted PowerFET array is disclosed. This slotted approach results in a dense PowerFET, a low Ron due to the slotted design, an oxide isolated process without any due extra steps other than the slots, lower capacitance, lower leakage, smaller die, improved heat transfer, improved electro-migration, lower ground resistance, less cross talk, drops the isolation diffusion and the sinker diffusion, mostly low temperature processing and provides double metal with single metal processing. Also disclosed is a method for integrating this vertical DMOS with CMOS, bipolar and BCD to provide an optimized small, efficient die using the buried power buss approach and these technologies.

    Abstract translation: 公开了一种用于提供高功率，低电阻，高效的垂直DMOS器件的器件。 该装置包括提供其上具有源体结构的半导体衬底。 该装置还包括源/体结构中的多个槽，并在多个槽内提供金属以形成多个结构。 公开了一种开槽的PowerFET阵列。 这种开槽方法导致密集的PowerFET，由于开槽设计而导致的低Ron，氧化物隔离工艺，除了槽之外没有任何额外的步骤，较低的电容，较低的泄漏，更小的管芯，改善的热传递，改善的电迁移， 降低接地电阻，减少串扰，降低隔离扩散和沉降扩散，多为低温处理，并提供单金属加工双金属。 还公开了一种用于将该垂直DMOS与CMOS，双极和BCD集成的方法，以使用掩埋功率总线方法和这些技术来提供优化的小型高效晶片。

    Power FET with embedded body pickup
    2.
    发明授权
    Power FET with embedded body pickup 有权
    具有嵌入式机身拾取功能的FET

    公开(公告)号：US07315052B2

    公开(公告)日：2008-01-01

    申请号：US11368092

    申请日：2006-03-02

    Applicant: Martin Alter

    Inventor： Martin Alter

    IPC: H01L29/76

    CPC classification number: H01L29/1083 ,  H01L29/4175 ,  H01L29/78

    Abstract: A power transistor formed on a semiconductor substrate and including a lateral array of polysilicon lines separated by alternating source and drain regions includes one or more body contact diffusion regions formed in the source regions where each body contact diffusion region has a length that extends to the edges of the two adjacent polysilicon lines, and one or more body pickup contacts where each body pickup contact is formed over a respective body contact diffusion region. In one embodiment, the body contact diffusion regions are formed in a fabrication process using ion implantation of dopants of a first type through a body diffusion mask. Each body contact diffusion region defined by an exposed area in the body diffusion mask has a drawn area that overlaps the respective two adjacent polysilicon lines.

    Abstract translation: 形成在半导体衬底上并且包括由交流的源极和漏极区分开的多晶硅线的横向阵列的功率晶体管包括形成在源区中的一个或多个体接触扩散区，其中每个体接触扩散区具有延伸到边缘的长度 的两个相邻多晶硅线，以及一个或多个身体拾取触点，其中每个身体拾取触点形成在相应的身体接触扩散区域上。 在一个实施例中，在使用通过身体扩散掩模的第一类型的掺杂剂的离子注入的制造工艺中形成体接触扩散区域。 由身体扩散掩模中的暴露区域限定的每个身体接触扩散区域具有与相应的两个相邻多晶硅线重叠的拉伸区域。

    Zener-like trim device in polysilicon
    4.
    发明授权
    Zener-like trim device in polysilicon 有权
    齐纳样多晶硅修边装置

    公开(公告)号：US06621138B1

    公开(公告)日：2003-09-16

    申请号：US10277638

    申请日：2002-10-21

    Applicant: Martin Alter

    Inventor： Martin Alter

    IPC: H01L2900

    CPC classification number: H01L23/5252 ,  H01L29/8605 ,  H01L29/866 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device includes a polysilicon layer in which a first region of a first conductivity type and a second region of a second conductivity type is formed. The first region and the second region form a p-n junction in the polysilicon layer. The semiconductor device further includes a first metallization region in electrical contact with the first region and a second metallization region in electrical contact with the second region. In operation, a low resistance path is formed between the first and second metallization region when a voltage or a current exceeding a predetermined threshold level is applied to the first or the second region. The voltage or current is applied for zap trimming of the p-n junction where the voltage or current exceeding a predetermined threshold level, together with the resulting current or resulting voltage, provides power sufficient to cause the low resistance path to be formed.

    Abstract translation: 半导体器件包括其中形成第一导电类型的第一区域和第二导电类型的第二区域的多晶硅层。 第一区域和第二区域在多晶硅层中形成p-n结。 半导体器件还包括与第一区域电接触的第一金属化区域和与第二区域电接触的第二金属化区域。 在操作中，当超过预定阈值电平的电压或电流施加到第一或第二区域时，在第一和第二金属化区域之间形成低电阻路径。 施加电压或电流用于p-n结的zap微调，其中电压或电流超过预定阈值电平以及所得到的电流或所得电压提供足以导致形成低电阻路径的功率。

    Selective substrate implant process for decoupling analog and digital grounds
    5.
    发明授权
    Selective substrate implant process for decoupling analog and digital grounds 有权
    用于解耦模拟和数字接地的选择性衬底植入工艺

    公开(公告)号：US06395591B1

    公开(公告)日：2002-05-28

    申请号：US09733543

    申请日：2000-12-07

    Applicant: Stephen McCormack ,  Martin Alter ,  Robert S. Wrathall ,  Carlos Alberto Laber

    Inventor： Stephen McCormack ,  Martin Alter ,  Robert S. Wrathall ,  Carlos Alberto Laber

    IPC: H01L218238

    CPC classification number: H01L27/092 ,  H01L21/761 ,  H01L21/823878 ,  H01L21/823892

    Abstract: An integrated circuit fabrication process includes a selective substrate implant process to effectively decouple a first power supply connection from a second power supply connection while providing immunity against parasitic effects. In one embodiment, the selective substrate implant process forms heavily doped p-type regions only under P-wells in which noise producing circuitry are built. The noisy ground connection for these P-wells are decoupled from the quiet ground connection for others P-wells not connected to any heavily doped regions and in which noise sensitive circuitry are built. The selective substrate implant process of the present invention has particular applications in forming CMOS analog integrated circuits where it is important to decouple the analog ground for sensitive analog circuitry from the often noisy digital grounds of the digital and power switching circuitry.

    Abstract translation: 集成电路制造工艺包括选择性衬底注入工艺，以有效地将第一电源连接与第二电源连接分离，同时提供对寄生效应的抗扰性。 在一个实施例中，选择性衬底注入工艺仅在构建噪声产生电路的P阱下形成重掺杂的p型区域。 这些P阱的噪声接地连接与静态接地连接分离，对于未连接到任何重掺杂区域并且其中构建噪声敏感电路的其他P阱。 本发明的选择性衬底注入工艺在形成CMOS模拟集成电路方面具有特别的应用，其中重要的是使敏感模拟电路的模拟地与数字和功率开关电路的经常噪声的数字接地分离。

    MOS Transistor Including Extended NLDD Source-Drain Regions For Improved Ruggedness
    6.
    发明申请
    MOS Transistor Including Extended NLDD Source-Drain Regions For Improved Ruggedness 审中-公开
    包括扩展NLDD源极 - 漏极区域的MOS晶体管，用于改善坚固性

    公开(公告)号：US20100032753A1

    公开(公告)日：2010-02-11

    申请号：US12578539

    申请日：2009-10-13

    Applicant: Martin Alter

    Inventor： Martin Alter

    IPC: H01L29/78 ,  H01L21/8236

    CPC classification number: H01L29/7833 ,  H01L29/1045 ,  H01L29/41725 ,  H01L29/41775 ,  H01L29/66575 ,  H01L29/66659 ,  H01L29/7835

    Abstract: A MOS transistor includes a conductive gate insulated from a semiconductor layer by a dielectric layer, first and second lightly-doped diffusion regions formed self-aligned to respective first and second edges of the conductive gate, a first diffusion region formed self-aligned to a first spacer, a second diffusion region formed a first distance away from the edge of a second spacer, a first contact opening and metallization formed above the first diffusion region, and a second contact opening and metallization formed above the second diffusion region. The first lightly-doped diffusion region remains under the first spacer. The second lightly-doped diffusion region remains under the second spacer and extends over the first distance to the second diffusion region. The distance between the first edge of the conductive gate to the first contact opening is the same as the distance between the second edge of the conductive gate to the second contact opening.

    Abstract translation: MOS晶体管包括通过电介质层与半导体层绝缘的导电栅极，与导电栅极的相应第一和第二边缘自对准形成的第一和第二轻掺杂扩散区域，形成为自对准到 第一间隔物，形成在第二间隔物的边缘第一距离处的第二扩散区域，形成在第一扩散区域上方的第一接触开口和金属化物，以及形成在第二扩散区域上方的第二接触开口和金属化物。 第一轻掺杂扩散区保留在第一间隔物下。 第二轻掺杂扩散区保留在第二间隔物下方并且延伸超过第一距离到第二扩散区。 导电栅极的第一边缘与第一接触开口之间的距离与导电栅极的第二边缘与第二接触开口之间的距离相同。

    Transistors fabricated using a reduced cost CMOS process
    7.
    发明授权
    Transistors fabricated using a reduced cost CMOS process 有权
    使用降低成本的CMOS工艺制造的N沟道MOS晶体管

    公开(公告)号：US07573098B2

    公开(公告)日：2009-08-11

    申请号：US11833138

    申请日：2007-08-02

    Applicant: Martin Alter

    Inventor： Martin Alter

    IPC: H01L29/78

    CPC classification number: H01L29/1083 ,  H01L21/8238 ,  H01L29/78

    Abstract: An NMOS transistor includes a semiconductor substrate of a first conductivity type, first and second well regions of a second conductivity type formed spaced apart in the substrate, a conductive gate formed over the region between the spaced apart first and second well regions where the region of the substrate between the spaced apart first and second well regions forms the channel region, dielectric spacers formed on the sidewalls of the conductive gate, first and second heavily doped source and drain regions of the second conductivity type formed in the semiconductor substrate and being self-aligned to the edges of the dielectric spacers. The first and second well regions extend from the respective heavily doped regions through an area under the spacers to the third well region. The first and second well regions bridge the source and drain regions to the channel region of the transistor formed by the third well.

    Abstract translation: NMOS晶体管包括在衬底中间隔开形成的第一导电类型的第二导电类型的第一和第二阱区的半导体衬底，形成在间隔开的第一和第二阱区之间的区域上的导电栅极， 在间隔开的第一和第二阱区域之间的衬底形成沟道区，形成在导电栅极的侧壁上的电介质间隔物，形成在半导体衬底中的第二和第二重掺杂的第二导电类型的源极和漏极区， 对准电介质间隔物的边缘。 第一和第二阱区域从相应的重掺杂区域延伸穿过垫片下面的区域到第三阱区域。 第一阱区和第二阱区将源区和漏区连接到由第三阱形成的晶体管的沟道区。

    High Voltage Metal-On-Passivation Capacitor
    8.
    发明申请
    High Voltage Metal-On-Passivation Capacitor 审中-公开
    高电压金属钝化电容器

    公开(公告)号：US20080185682A1

    公开(公告)日：2008-08-07

    申请号：US11671882

    申请日：2007-02-06

    Applicant: Martin Alter

    Inventor： Martin Alter

    IPC: H01L29/92

    CPC classification number: H01G4/33 ,  H01G4/228 ,  H01G4/38 ,  H01L23/5223 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A capacitor is formed in an integrated circuit where the integrated circuit is fabricated using a fabrication process having multiple metal layers with the topmost metal layer being passivated by a passivation layer. The capacitor includes a first metal pad formed underneath the passivation layer using the topmost metal layer of the integrated circuit where the first metal pad forming the first conductive plate of the capacitor, and a second metal pad formed on the top of the passivation layer with the second metal pad being in vertical alignment with the first metal pad. The second metal pad forms the second conductive plate of the capacitor and the second metal pad is formed without an overlying passivation layer. The passivation layer sandwiched between the first metal pad and the second metal pad forms the dielectric of the capacitor.

    Abstract translation: 在集成电路中形成电容器，其中使用具有多个金属层的制造工艺来制造集成电路，其中最顶层金属层被钝化层钝化。 电容器包括使用集成电路的最顶层金属层形成在钝化层下方的第一金属焊盘，其中形成电容器的第一导电板的第一金属焊盘和形成在钝化层的顶部上的第二金属焊盘 第二金属垫与第一金属垫垂直对准。 第二金属焊盘形成电容器的第二导电板，第二金属焊盘形成而没有上覆的钝化层。 夹在第一金属焊盘和第二金属焊盘之间的钝化层形成电容器的电介质。

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