发明授权
- 专利标题: Methods of testing for shorts in programmable logic devices using relative quiescent current measurements
- 专利标题(中): 使用相对静态电流测量测试可编程逻辑器件中短路的方法
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申请号: US10644158申请日: 2003-08-20
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公开(公告)号: US06920621B1公开(公告)日: 2005-07-19
- 发明人: Shahin Toutounchi , Erik V. Chmelar , Robert W. Wells
- 申请人: Shahin Toutounchi , Erik V. Chmelar , Robert W. Wells
- 申请人地址: US CA San Jose
- 专利权人: Xilinx, Inc.
- 当前专利权人: Xilinx, Inc.
- 当前专利权人地址: US CA San Jose
- 代理商 Lois D. Cartier
- 主分类号: G01R31/30
- IPC分类号: G01R31/30 ; G06F11/24 ; G06F17/50
摘要:
Methods of testing for shorts (e.g., bridging defects) between interconnect lines in an integrated circuit. For example, in a design implemented in a programmable logic device (PLD), some interconnect lines are used and others are unused. To test for shorts between the used and unused interconnect lines, both used and unused interconnect lines are driven to a first logic level, and the leakage current is measured. The used interconnect lines are driven to a second logic level, while the unused lines remain at the first logic level. The current is again measured, and the difference between the two measurements is determined. If the difference exceeds a predetermined threshold, the device design combination is rejected. Some embodiments provide methods of testing for shorts between used and unused interconnect lines for a design targeted to a partially defective PLD.