Invention Grant
US06925550B2 Speculative scheduling of instructions with source operand validity bit and rescheduling upon carried over destination operand invalid bit detection
失效
具有源操作数有效位的指令的推测调度，以及在目的地操作数无效位检测上重新调度
- Patent Title: Speculative scheduling of instructions with source operand validity bit and rescheduling upon carried over destination operand invalid bit detection
- Patent Title (中): 具有源操作数有效位的指令的推测调度，以及在目的地操作数无效位检测上重新调度
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Application No.: US10040223Application Date: 2002-01-02
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Publication No.: US06925550B2Publication Date: 2005-08-02
- Inventor: Eric Sprangle , Michael J. Haertel , David J. Sager
- Applicant: Eric Sprangle , Michael J. Haertel , David J. Sager
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: G06F9/38
- IPC: G06F9/38
Abstract:
A method and apparatus to execute data speculative instructions in a processor comprising at least one source register, each source register comprising a bit to indicate validity of data in the at least one source register. A data validity circuit coupled to the one or more source registers to determine the validity of the data in the source registers, and to indicate the validity of the data in a destination register based upon the validity bit in the at least one source register. The processor optionally comprising a checker unit to retire those instructions from the execution unit which write valid data to the destination register, and to re-schedules those instructions for execution which write invalid data to the destination register.
Public/Granted literature
- US20030126417A1 Method and apparatus to execute instructions in a processor Public/Granted day:2003-07-03
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