发明授权
- 专利标题： Apparatus for controlling and supplying in phase clock signals to components of an integrated circuit with a multiprocessor architecture
- 专利标题（中）： 用于控制和提供相位时钟信号到具有多处理器架构的集成电路的组件的装置
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申请号： US09973888申请日： 2001-10-11
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公开(公告)号： US06928575B2公开(公告)日： 2005-08-09
- 发明人: Kazuhiro Okabayashi , Minoru Okamoto , Shinichi Marui
- 申请人： Kazuhiro Okabayashi , Minoru Okamoto , Shinichi Marui
- 申请人地址： JP Osaka
- 专利权人： Matsushita Electric Industrial Co., Ltd.
- 当前专利权人： Matsushita Electric Industrial Co., Ltd.
- 当前专利权人地址： JP Osaka
- 代理机构： McDermott Will & Emery LLP
- 优先权： JP2000-311580 20001012
- 主分类号： G11C7/22
- IPC分类号： G11C7/22 ; G06F1/12
摘要：
A first processor, a second processor, a memory and a clock supply unit are integrated together on a single chip. The first processor operates synchronously with a first internal clock signal. The second processor operates synchronously with a second internal clock signal. The memory operates synchronously with a third internal clock signal. The clock supply unit generates three clock signals, which are in phase with each other, from an external clock signal and supplies those clock signals as the first, second and third internal clock signals. The first and second processors share the memory via a data bus. Each of the processors has an internal reset signal.
公开/授权文献
- US20020046356A1 Integrated circuit with multiprocessor architecture 公开/授权日：2002-04-18
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