公开(公告)号：US20050163233A1

公开(公告)日：2005-07-28

申请号：US11022811

申请日：2004-12-28

申请人： Ryutaro Yamanaka ,  Hidetoshi Suzuki ,  Hideyuki Kabuo ,  Minoru Okamoto ,  Kevin Stone

发明人： Ryutaro Yamanaka ,  Hidetoshi Suzuki ,  Hideyuki Kabuo ,  Minoru Okamoto ,  Kevin Stone

IPC分类号： G06F11/10 ,  H03M13/23 ,  H03M13/41 ,  H04L1/00 ,  H04B14/04

CPC分类号： H03M13/6502 ,  H03M13/3961 ,  H03M13/4107 ,  H03M13/4169 ,  H03M13/6561 ,  H03M13/6563 ,  H03M13/6569

摘要： A digital signal processor includes a functional unit configured to execute instructions. The functional unit determines a first minimum data of a first data and a second data, in parallel with a determination of a second minimum data of a third data and a fourth data. The functional unit outputs processed data including the first minimum data and the second minimum data. Each bit length of the first minimum data and the second minimum data is equal to n bits in length. A bit length of the processed data is equal to 2n bits in length.

摘要翻译： 数字信号处理器包括被配置为执行指令的功能单元。 功能单元与第三数据和第四数据的第二最小数据的确定并行地确定第一数据和第二数据的第一最小数据。 功能单元输出包括第一最小数据和第二最小数据的处理数据。 第一最小数据和第二最小数据的每个位长度等于n位长度。 处理数据的位长度等于2n位长。

公开(公告)号：US06751773B2

公开(公告)日：2004-06-15

申请号：US09833061

申请日：2001-04-12

申请人： Kazuhiro Okabayashi ,  Minoru Okamoto ,  Masayuki Yamasaki

发明人： Kazuhiro Okabayashi ,  Minoru Okamoto ,  Masayuki Yamasaki

IPC分类号： H03M1303

CPC分类号： H03M13/23

摘要： A coding apparatus includes shift register, input register and logical operation section. The shift register performs bit shifting on an input bit sequence and stores one bit of the input bit sequence after another. The input register stores coefficients of terms on respective orders of a generator polynomial. The logical operation section obtains logical products of the respective bits stored on the shift register and associated bits stored on the input register and a logical product of each one bit input to the shift register and an associated bit stored on the input register so that the earlier a bit of the input bit sequence was input, the higher-order one of the coefficients in the terms of the polynomial the input bit is associated with. Next, the logical operation section derives an exclusive logical sum of the products and then outputs the sum as a bit of a code sequence.

摘要翻译： 编码装置包括移位寄存器，输入寄存器和逻辑运算部。 移位寄存器在输入位序列上执行位移位，并将输入位序列的一位相继存储。 输入寄存器存储关于生成多项式的各个阶的项的系数。 逻辑运算部分获得存储在移位寄存器上的相应位的逻辑积和存储在输入寄存器上的相关位以及输入到移位寄存器的每一位的逻辑积和存储在输入寄存器上的关联位， 输入一位输入比特序列，输入比特关联的多项式项中的系数中的高阶一个。 接下来，逻辑运算部分导出乘积的异或逻辑和，然后输出和作为代码序列的位。

公开(公告)号：US06477661B2

公开(公告)日：2002-11-05

申请号：US09974807

申请日：2001-10-12

申请人： Ryutaro Yamanaka ,  Hidetoshi Suzuki ,  Hideyuki Kabuo ,  Minoru Okamoto ,  Kevin Mark Stone

发明人： Ryutaro Yamanaka ,  Hidetoshi Suzuki ,  Hideyuki Kabuo ,  Minoru Okamoto ,  Kevin Mark Stone

IPC分类号： G06F1100

CPC分类号： H03M13/6502 ,  H03M13/3961 ,  H03M13/4107 ,  H03M13/4169 ,  H03M13/6561 ,  H03M13/6563 ,  H03M13/6569

摘要： A method of operating a digital signal processor is provided. The digital signal processor may be provided as a radio communication mobile station, a radio communication base station apparatus, or a CDMA radio communication system. Each path metric PM1 and PM0 of an old state is added to each branch metric BM1 and BM0 separately. A path metric of a new state N is formed by comparing the value of PM1+BM1 to the value of PM0+BM0. A path metric of a new state N+2k−2 is formed by comparing the value of PM1+BM0 to PM0+BM1.

摘要翻译： 提供了一种操作数字信号处理器的方法。 数字信号处理器可以被提供为无线电通信移动台，无线电通信基站装置或CDMA无线电通信系统。 将旧状态的每个路径度量PM1和PM0分别添加到每个分支量度BM1和BM0。 通过将PM1 + BM1的值与PM0 + BM0的值进行比较来形成新状态N的路径度量。 通过将PM1 + BM0的值与PM0 + BM1进行比较来形成新状态N + 2k-2的路径度量。

公开(公告)号：US06289429B1

公开(公告)日：2001-09-11

申请号：US08812711

申请日：1997-03-06

申请人： Minoru Okamoto

发明人： Minoru Okamoto

IPC分类号： G06F1200

摘要： A memory device including a first memory and a second memory. A first processor generates a first address for defining a location to be accessed in the first memory and a second address for defining a location to be accessed in the second memory. A second processor generates a third address. A memory control section controls access to the first memory and access to the second memory. The memory control section includes an address conversion section for converting the third address so as to represent either one of the first address and the second address.

公开(公告)号：US20120293526A1

公开(公告)日：2012-11-22

申请号：US13560682

申请日：2012-07-27

申请人： Minoru OKAMOTO ,  Ryutaro YAMANAKA ,  Kazuhiro OKABAYASHI ,  Yukihiro SASAGAWA

发明人： Minoru OKAMOTO ,  Ryutaro YAMANAKA ,  Kazuhiro OKABAYASHI ,  Yukihiro SASAGAWA

IPC分类号： G09G3/36 ,  G09G5/36

CPC分类号： G09G3/2096 ,  G09G3/2003 ,  G09G3/3611 ,  G09G2340/02 ,  G09G2340/145

摘要： A panel control device includes a programmable array. This programmable array operates in accordance with a configuration code and includes a plurality of first-class elements and at least one second-class element. This provides a panel control device requiring a small circuit area, being suitable for system-on-chip (SoC) mounting, and driving a liquid crystal display device having various specifications also in the future.

摘要翻译： 面板控制装置包括可编程阵列。 该可编程阵列根据配置代码进行操作并且包括多个第一类元素和至少一个第二类元素。 这提供了一种面板控制装置，其需要小的电路面积，适用于系统级芯片（SoC）安装，并且在将来也驱动具有各种规格的液晶显示装置。

公开(公告)号：US20100206808A1

公开(公告)日：2010-08-19

申请号：US12675600

申请日：2008-08-26

申请人： Katsuhiko Maeda ,  Minoru Okamoto

发明人： Katsuhiko Maeda ,  Minoru Okamoto

IPC分类号： C02F3/12 ,  C12N9/24

CPC分类号： C02F3/342 ,  C02F3/006 ,  C02F3/341 ,  C02F3/348 ,  C02F2103/20 ,  C02F2103/22 ,  C02F2103/26 ,  C02F2103/32 ,  C02F2209/36 ,  C02F2303/06

摘要： Excess sludge production in a bioreactor of a wastewater treatment plant in which excess sludge is being produced is reduced by adding an activated sludge material having a chitinase specific activity of at least 150 Units/g-MLSS and a pectinase specific activity of at least 120 Units/g-MLSS to the bioreactor. After the addition of the activated sludge material, the bioreactor is controlled by adding the activated sludge material when any one of the chitinase activity, the pectinase activity, and the protease specific of the sludge in the bioreactor drops below the lower limits of 50 Units/L, 40 Units/L, and 0.3 Units/L, respectively.

摘要翻译： 通过添加具有至少150单位/ g-MLSS的几丁质酶比活性和至少120单位的果胶酶特异性活性的活性污泥材料，可以减少生产过剩污泥的废水处理厂的生物反应器中的过剩污泥生产 / g-MLSS到生物反应器。 添加活性污泥材料后，生物反应器中的几丁质酶活性，果胶酶活性和污泥蛋白酶特异性中的任何一种下降到50单位/ L，40单位/ L，0.3单位/ L。

公开(公告)号：US07774281B2

公开(公告)日：2010-08-10

申请号：US11152085

申请日：2005-06-15

申请人： Minoru Okamoto ,  Katsuhiko Ueda ,  Shirou Yoshioka ,  Tetsuji Kishi

发明人： Minoru Okamoto ,  Katsuhiko Ueda ,  Shirou Yoshioka ,  Tetsuji Kishi

IPC分类号： G06F21/00

CPC分类号： G06F21/10

摘要： A terminal device transmits device information thereof and a request for acquiring information contents to a contents distribution device. The contents distribution device generates a request for distributing a program for materializing the information contents in the terminal device based on the information contents designated in the acquisition request and the device information, and transmits a license request for using a function standard required for realizing the function to a license management device. The license management device receives the usage license request and correspondingly transmits an authorization for using the function standard to the program distribution device and the contents distribution device. The program distribution device transmits the program to the terminal device only when the usage authorization is received. The contents distribution device transmits the information contents to the terminal device only when the usage authorization is received.

摘要翻译： 终端装置向内容发布装置发送其设备信息和获取信息内容的请求。 内容分发装置根据获取请求中指定的信息内容和设备信息生成分发用于实现终端装置中的信息内容的程序的请求，并发送使用实现功能所需的功能标准的许可请求 到许可证管理设备。 许可证管理装置接收使用许可证请求，并相应地向程序发布装置和内容分发装置发送使用功能标准的授权。 程序分发装置仅在接收到使用授权时将程序发送到终端装置。 内容分发装置仅在接收到使用授权时才将该信息内容发送到终端装置。

公开(公告)号：US07536289B2

公开(公告)日：2009-05-19

申请号：US11071465

申请日：2005-03-04

申请人： Kazuhiro Okabayashi ,  Minoru Okamoto

发明人： Kazuhiro Okabayashi ,  Minoru Okamoto

IPC分类号： G06F17/50

CPC分类号： G06F17/5054

摘要： A method of configuring an information processing system according to the present invention, in an information processing system for realizing one or a plurality of applications, comprises, a step of modeling all of the applications for each certain process level and inputting the models, a step of inputting parameters representing invariability for the inputted models, a step of using the models of the applications and the parameters representing invariability as inputted information and comparing the parameters representing invariability to a boundary condition, and a step of allocating one of the application models to programmable logic and another of the application models to an exclusive-use hardware based on a result of the comparison.

摘要翻译： 一种根据本发明的信息处理系统的配置方法，在用于实现一个或多个应用的​​信息处理系统中，包括：对于每个确定的处理级别并输入模型的所有应用进行建模的步骤，步骤 输入表示输入模型的不变性的参数的步骤，使用应用模型和表示不变性的参数作为输入信息并将表示不变性的参数与边界条件进行比较的步骤，以及将应用模型之一分配给可编程 逻辑和另一个应用模型基于比较结果的专用硬件。

公开(公告)号：US20080072129A1

公开(公告)日：2008-03-20

申请号：US11929126

申请日：2007-10-30

申请人： Ryutaro YAMANAKA ,  Hidetoshi SUZUKI ,  Hideyuki KABUO ,  Minoru OKAMOTO ,  Kevin STONE

发明人： Ryutaro YAMANAKA ,  Hidetoshi SUZUKI ,  Hideyuki KABUO ,  Minoru OKAMOTO ,  Kevin STONE

IPC分类号： H03M13/03

CPC分类号： H03M13/6502 ,  H03M13/3961 ,  H03M13/4107 ,  H03M13/4169 ,  H03M13/6561 ,  H03M13/6569

摘要： A digital signal processor includes an instruction executer configured to execute instructions. The instruction executer determines a first minimum data of a first data and a second data, in parallel with a determination of a second minimum data of a third data and a fourth data. The instruction executer outputs a processed data including the first minimum data and the second minimum data. A bit length of the first minimum data is equal to n bits in length. A bit length of the second minimum data is equal to n bits in length. A bit length of the processed data is equal to at least 2n bits in length.

摘要翻译： 数字信号处理器包括被配置为执行指令的指令执行器。 指令执行器与第三数据和第四数据的第二最小数据的确定并行地确定第一数据和第二数据的第一最小数据。 指令执行器输出包括第一最小数据和第二最小数据的处理数据。 第一最小数据的位长度等于n位长度。 第二最小数据的位长度等于n位长度。 经处理的数据的位长度等于至少2n位长度。

公开(公告)号：US20080061834A1

公开(公告)日：2008-03-13

申请号：US11667302

申请日：2006-10-02

申请人： Tatsuya Tetsukawa ,  Minoru Okamoto ,  Shinichi Marui

发明人： Tatsuya Tetsukawa ,  Minoru Okamoto ,  Shinichi Marui

IPC分类号： H03K19/00

CPC分类号： H03K19/1774 ,  G06F17/5054

摘要： A plurality of logic element groups LEG11 to LEG33 respectively include at least one logic element as a component of a reconfigurable semiconductor integrated circuit. Between any logic element groups engaging in data transmission/reception, e.g., LEG11 and LEG12, clock out terminal and clock in terminal are connected via a line while data out terminal and data in terminal are connected via a delay element 101. The logic element groups LEG11 to LEG33 are therefore independent of one another in terms of timing design. Thus, if redesign is necessary for a semiconductor integrated circuit completed with a plurality of logic element groups, only a new circuit may be designed and connected to an existing circuit, or an unnecessary logic element group may just be removed, to complete a new semiconductor integrated circuit.

摘要翻译： 多个逻辑元件组LEG 11至LEG 33分别包括作为可重构半导体集成电路的组件的至少一个逻辑元件。 在进行数据发送/接收的任何逻辑元件组（例如LEG 11和LEG 12）之间，终端中的时钟输出端和时钟通过线连接，而终端中的数据输出端和数据通过延迟元件101连接。逻辑 元素组LEG 11至LEG 33在时序设计方面因此彼此独立。 因此，如果对于用多个逻辑元件组完成的半导体集成电路进行重新设计，则可以仅设计新的电路并将其连接到现有的电路，或者可以去除不必要的逻辑元件组以完成新的半导体 集成电路。