Invention Grant
US06931296B2 Algorithms tunning for dynamic lot dispatching in wafer and chip probing
失效
调整晶圆和芯片探测中的动态批量调度的算法
- Patent Title: Algorithms tunning for dynamic lot dispatching in wafer and chip probing
- Patent Title (中): 调整晶圆和芯片探测中的动态批量调度的算法
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Application No.: US10672403Application Date: 2003-09-26
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Publication No.: US06931296B2Publication Date: 2005-08-16
- Inventor: Ta-Chin Lin , Yi-Feng Huang , Fu-Kang Lai , Jen-Chih Hsiao
- Applicant: Ta-Chin Lin , Yi-Feng Huang , Fu-Kang Lai , Jen-Chih Hsiao
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Thomas, Kayden, Horstemeyer & Risley
- Main IPC: G05B19/418
- IPC: G05B19/418 ; G06F19/00

Abstract:
A method and system for flexible, comprehensive, on-line, real-time dynamic lot dispatching in a semiconductor test foundry based on a two-phased, event-driven dispatching system structure. An adjustable priority formula and tuned algorithms integrated with PROMIS' constraint function give a nearly optimum dispatching list on any tester at any time with reduced mistake operations. Exception rules take care of special events to improve daily dispatching manual effort. This invention can automatically dispatch engineering lots according to engineering lots' capacity of Testing, solve conflict between wafer and package lots, efficiently reduce tester setup times, replace daily manual-dispatching sheet and keep a high CLIP rate while fully following MPS.
Public/Granted literature
- US20050071031A1 Algorithms tunning for dynamic lot dispatching in wafer and chip probing Public/Granted day:2005-03-31
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