- 专利标题: Semiconductor memory circuit
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申请号: US10190480申请日: 2002-07-09
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公开(公告)号: US06934210B2公开(公告)日: 2005-08-23
- 发明人: Takesada Akiba , Shigeki Ueda , Toshikazu Tachibana , Masashi Horiguchi
- 申请人: Takesada Akiba , Shigeki Ueda , Toshikazu Tachibana , Masashi Horiguchi
- 申请人地址: JP Tokyo JP Chiba
- 专利权人: Renesas Technology Corporation,Hitachi Device Engineering Co., Ltd.
- 当前专利权人: Renesas Technology Corporation,Hitachi Device Engineering Co., Ltd.
- 当前专利权人地址: JP Tokyo JP Chiba
- 代理机构: Reed Smith LLP
- 代理商 Stanley P. Fisher, Esq.; Juan Carlos A. Marquez, Esq.
- 优先权: JP2001-261123 20010830
- 主分类号: G11C11/407
- IPC分类号: G11C11/407 ; G11C5/14 ; G11C11/401 ; G11C11/403 ; G11C11/406 ; G11C11/4074 ; G11C11/409 ; G11C29/08 ; G11C7/00 ; G11C7/04
摘要:
The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.
公开/授权文献
- US20030043680A1 Semiconductor memory circuit 公开/授权日:2003-03-06