Invention Grant
- Patent Title: Cache-line reuse-buffer
- Patent Title (中): 缓存行重用缓冲区
-
Application No.: US10121524Application Date: 2002-04-12
-
Publication No.: US06938126B2Publication Date: 2005-08-30
- Inventor: Alejandro Ramirez , Edward Grochowski , Hong Wang , John Shen
- Applicant: Alejandro Ramirez , Edward Grochowski , Hong Wang , John Shen
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor and Zafman
- Main IPC: G06F9/38
- IPC: G06F9/38 ; G06F12/08 ; G06F12/00

Abstract:
A method, apparatus, and system that compares a current fetch request having a first start address and length associated with the current fetch request to a second start address of the next fetch request, determines whether the content already loaded in a buffer will be used to at least partially fulfill the next fetch request based upon the comparison, and inhibits access to an instruction cache based upon the comparison.
Public/Granted literature
- US20030196044A1 Cache-line reuse-buffer Public/Granted day:2003-10-16
Information query