The semiconducting memory device comprises a non-volatile programmable and electrically erasable memory cell with a single layer of grid material and comprising a floating grid transistor and a control grid, within an active semiconducting area formed in a region of the substrate and delimited by an isolation region. The layer of grid material EG, FL P2 in which the floating grid FG is made extends integrall above the active area ZA without overlapping part of the isolation region STI, and the transistor is electrically isolated from the control grid CG by PN junctions that will be reverse biased.