发明授权
US06944714B2 Method and apparatus for saving microprocessor power when sequentially accessing the microprocessor's instruction cache
失效
在顺序访问微处理器的指令高速缓存时节省微处理器电力的方法和装置
- 专利标题: Method and apparatus for saving microprocessor power when sequentially accessing the microprocessor's instruction cache
- 专利标题(中): 在顺序访问微处理器的指令高速缓存时节省微处理器电力的方法和装置
-
申请号: US10209473申请日: 2002-07-30
-
公开(公告)号: US06944714B2公开(公告)日: 2005-09-13
- 发明人: Gregg B. Lesarte , John W. Bockhaus
- 申请人: Gregg B. Lesarte , John W. Bockhaus
- 申请人地址: US TX Houston
- 专利权人: Hewlett-Packard Development Company, L.P.
- 当前专利权人: Hewlett-Packard Development Company, L.P.
- 当前专利权人地址: US TX Houston
- 代理商 John Pessetto
- 主分类号: G06F1/32
- IPC分类号: G06F1/32 ; G06F12/08 ; G06F12/00
摘要:
An embodiment of the invention provides a circuit and method for reducing power in multi-way set associative arrays. A control circuit detects when the next cache access will be taken from the same cache way that the previous cache access was taken from. If the next cache access is taken from the same cache way as the previous cache access, the control circuit signals all the cache ways, except the cache way that was previously accessed, to not access information from their arrays. The control circuit also signals the tag arrays to not access their information and disables power to all the compare circuits. In this manner, power may be reduced when sequentially accessing information from one cache way in a multi-way set associative array.
公开/授权文献
信息查询