发明授权
US06950924B2 Passing decoded instructions to both trace cache building engine and allocation module operating in trace cache or decoder reading state
失效
将解码的指令传递到跟踪高速缓存构建引擎和在跟踪缓存或解码器读取状态中操作的分配模块
- 专利标题： Passing decoded instructions to both trace cache building engine and allocation module operating in trace cache or decoder reading state
- 专利标题（中）： 将解码的指令传递到跟踪高速缓存构建引擎和在跟踪缓存或解码器读取状态中操作的分配模块
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申请号： US10032565申请日： 2002-01-02
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公开(公告)号： US06950924B2公开(公告)日： 2005-09-27
- 发明人: John Alan Miller , Stephan Jourdan
- 申请人： John Alan Miller , Stephan Jourdan
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理商 Shireen I. Bacon
- 主分类号： G06F9/00
- IPC分类号： G06F9/00 ; G06F9/06 ; G06F9/38 ; G06F15/00
摘要：
A system and method of managing processor instructions provides enhanced performance. The system and method provide for decoding a first instruction into a plurality of operations with a decoder. A first copy of the operations is passed from the decoder to a build engine associated with a trace cache. The system and method further provide for passing a second copy of the operation from the decoder directly to a back end allocation module such that the operations bypass the build engine and the allocation module is in a decoder reading state.
公开/授权文献
- US20030126418A1 Trace cache bypassing 公开/授权日：2003-07-03
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