发明授权
US06952363B2 Semiconductor memory device with selectively connectable segmented bit line member and method of driving the same
有权
具有可选择地连接的分段位线构件的半导体存储器件及其驱动方法
- 专利标题: Semiconductor memory device with selectively connectable segmented bit line member and method of driving the same
- 专利标题(中): 具有可选择地连接的分段位线构件的半导体存储器件及其驱动方法
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申请号: US10785185申请日: 2004-02-25
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公开(公告)号: US06952363B2公开(公告)日: 2005-10-04
- 发明人: Tae-Joong Song , Tae-Hyoung Kim
- 申请人: Tae-Joong Song , Tae-Hyoung Kim
- 申请人地址: KR Gyeonggi-do
- 专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人地址: KR Gyeonggi-do
- 代理机构: Harness, Dickey & Pierce, PLC
- 优先权: KR10-2003-0034362 20030529
- 主分类号: G11C11/41
- IPC分类号: G11C11/41 ; G11C7/00 ; G11C7/12 ; G11C7/18 ; G11C8/12 ; G11C8/16 ; G11C11/00 ; G11C11/413
摘要:
A semiconductor memory device, that reduces load capacitance of write-only bit lines, may include: a first bit cell array block, in which bit cells thereof are defined by intersections of first bit lines and first word lines, the first bit lines being arranged as pairs of first signal lines and second signal lines, respectively; a second bit cell array block, in which bit cells thereof are defined by intersections of second bit lines and second word lines, the second bit lines being arranged as pairs of third signal lines and the second signal lines; respectively; a block division circuit operable to generate and output block division control signals; and a write bit line divider circuit operable to either open-circuit or connect together the first signal lines and the third signal lines, respectively, according to the block division control signals.