发明授权
- 专利标题: Error detection in dynamic logic circuits
- 专利标题(中): 动态逻辑电路中的错误检测
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申请号: US10150847申请日: 2002-05-17
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公开(公告)号: US06954912B2公开(公告)日: 2005-10-11
- 发明人: Pranjal Srivastava , Ajay Naini , Atul Dhablania
- 申请人: Pranjal Srivastava , Ajay Naini , Atul Dhablania
- 申请人地址: JP Kawasaki
- 专利权人: Fujitsu Limited
- 当前专利权人: Fujitsu Limited
- 当前专利权人地址: JP Kawasaki
- 代理机构: Fenwick & West LLP
- 主分类号: G06F11/18
- IPC分类号: G06F11/18 ; G01R31/317 ; G01R31/3183 ; G01R31/3185 ; H03K19/096 ; G06F17/50
摘要:
Error detection apparatus and methods for dynamic logic are provided. Circuit errors are detected by comparing true and complement signals to ensure they are in fact complementary signals. A pseudocomplement technique is used to implement an adder in which distinct logic cones generate the true and complement carry signals. Other embodiments comprising additional features, such as shared logic cone decomposition, are also provided.
公开/授权文献
- US20030217307A1 Error detection in dynamic logic circuits 公开/授权日:2003-11-20