发明授权
US06960501B2 Method of manufacturing a semiconductor memory device having a non-volatile memory cell portion with single misfet transistor type memory cells and a peripheral circuit portion with misfets
失效
具有具有单个失配晶体管型存储单元的非易失性存储单元部分和具有缺陷的外围电路部分的半导体存储器件的制造方法
- 专利标题: Method of manufacturing a semiconductor memory device having a non-volatile memory cell portion with single misfet transistor type memory cells and a peripheral circuit portion with misfets
- 专利标题(中): 具有具有单个失配晶体管型存储单元的非易失性存储单元部分和具有缺陷的外围电路部分的半导体存储器件的制造方法
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申请号: US10819205申请日: 2004-04-07
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公开(公告)号: US06960501B2公开(公告)日: 2005-11-01
- 发明人: Kazuhiro Komori , Toshiaki Nishimoto , Satoshi Meguro , Hitoshi Kume , Yoshiaki Kamigaki
- 申请人: Kazuhiro Komori , Toshiaki Nishimoto , Satoshi Meguro , Hitoshi Kume , Yoshiaki Kamigaki
- 申请人地址: JP Tokyo
- 专利权人: Renesas Technology Corp.
- 当前专利权人: Renesas Technology Corp.
- 当前专利权人地址: JP Tokyo
- 代理机构: Antonelli, Terry, Stout and Kraus, LLP.
- 优先权: JP63-284587 19881109
- 主分类号: H01L21/8247
- IPC分类号: H01L21/8247 ; H01L27/06 ; H01L27/105 ; H01L27/115 ; H01L29/788 ; H01L29/792 ; H01L21/8238 ; H01L21/336
摘要:
A semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions serving as the source and drain regions, respectively. In accordance with the method of manufacture thereof, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but with the second semiconductor region having a lower dose thereof so that the first semiconductor region formed attains a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. The device and method therefor further feature the formation of MISFETs of peripheral circuits.
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