发明授权
US06961271B2 Memory device in which memory cells having complementary data are arranged
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具有互补数据的存储单元被布置的存储器件
- 专利标题: Memory device in which memory cells having complementary data are arranged
- 专利标题(中): 具有互补数据的存储单元被布置的存储器件
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申请号: US10620022申请日: 2003-07-14
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公开(公告)号: US06961271B2公开(公告)日: 2005-11-01
- 发明人: Byung-Gil Jeon , Ki-Nam Kim , Mun-Kyu Choi
- 申请人: Byung-Gil Jeon , Ki-Nam Kim , Mun-Kyu Choi
- 申请人地址: KR Suwon-si
- 专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人地址: KR Suwon-si
- 代理机构: Marger Johnson & McCollom, P.C.
- 优先权: KR10-2002-0054169 20020909
- 主分类号: G11C11/409
- IPC分类号: G11C11/409 ; G11C5/06 ; G11C11/404 ; G11C11/405 ; G11C7/00
摘要:
A memory cell array block has unit memory cells comprised of pairs of memory cells, each of have a memory cell and a complementary memory cell. A second unit memory cell is interleaved with the first unit memory cell, a fourth unit memory cell is interleaved with a third unit memory cell. First and second sense amplifiers are disposed over and under the array block, respectively. The first switch connects bitlines coupled to the first unit memory cell with the first sense amplifier and connects bitlines coupled to the second unit memory cell with the second sense amplifier. The second switch connects bitlines coupled to the third unit memory cell with the first sense amplifier and connects bitlines coupled to the fourth unit memory cell with the second sense amplifier. A selected unit memory cell is selectively connected with a sense amplifier, decreasing the number of sense amplifiers.
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