A Factorized Power Architecture (“FPA”) method and apparatus for supplying power to highly transient loads such as microprocessors includes a front end power regulator (“PRM) which provides a controlled DC bus voltage which is converted to the desired load voltage using a DC voltage transformation module (“VTM”) at the point of load. The VTM converts the DC bus voltage to the DC voltage required by the load using a fixed transformation ratio K=Vout/Vin where Vin>Vout and with a low output resistance. The response time of the VTM, TVTM is less than the response time of the PRM, TPRM. A first capacitance, C1, across the load is made large enough to support the microprocessor current requirement within a time scale, T1, which is preferably greater than or equal to the characteristic open-loop response time of the VTM by itself, TVTM. A second capacitance, C2, at the input of the VTM is made large enough to support the microprocessor current requirement within a time scale, T2, which is preferably greater than or equal to the closed-loop response time of the front end power regulator, TPRM. Feedback may be provided from a feedback controller at the point of load to the front end or to upstream, on-board power regulator modules (“PRMs”) to achieve precise regulation. The VTM may convert power bi-directionally to return power to the bus during a “load dump.” Energy storage at the input to the VTM is greater than energy storage at the load.